2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
23 * @version $Id: bearch_amd64.c 26909 2010-01-05 15:56:54Z matze $
27 #include "pseudo_irg.h"
39 #include "../bearch.h"
40 #include "../benode.h"
41 #include "../belower.h"
42 #include "../besched.h"
44 #include "../bemodule.h"
45 #include "../begnuas.h"
46 #include "../belistsched.h"
47 #include "../beflags.h"
48 #include "../bespillslots.h"
50 #include "bearch_amd64_t.h"
52 #include "amd64_new_nodes.h"
53 #include "gen_amd64_regalloc_if.h"
54 #include "amd64_transform.h"
55 #include "amd64_emitter.h"
57 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
59 static arch_irn_class_t amd64_classify(const ir_node *irn)
65 static ir_entity *amd64_get_frame_entity(const ir_node *node)
67 if (is_amd64_FrameAddr(node)) {
68 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
71 } else if (is_amd64_Store(node)) {
72 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
75 } else if (is_amd64_Load(node)) {
76 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
81 /* TODO: return the ir_entity assigned to the frame */
85 static void amd64_set_frame_entity(ir_node *node, ir_entity *ent)
89 /* TODO: set the ir_entity assigned to the frame */
93 * This function is called by the generic backend to correct offsets for
94 * nodes accessing the stack.
96 static void amd64_set_frame_offset(ir_node *irn, int offset)
98 if (is_amd64_FrameAddr(irn)) {
99 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
100 attr->fp_offset += offset;
102 } else if (is_amd64_Store(irn)) {
103 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
104 attr->fp_offset += offset;
106 } else if (is_amd64_Load(irn)) {
107 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
108 attr->fp_offset += offset;
113 static int amd64_get_sp_bias(const ir_node *irn)
119 /* fill register allocator interface */
121 static const arch_irn_ops_t amd64_irn_ops = {
124 amd64_get_frame_entity,
125 amd64_set_frame_entity,
126 amd64_set_frame_offset,
128 NULL, /* get_inverse */
129 NULL, /* get_op_estimated_cost */
130 NULL, /* possible_memory_operand */
131 NULL, /* perform_memory_operand */
137 * Transforms the standard firm graph into
140 static void amd64_prepare_graph(void *self)
142 amd64_code_gen_t *cg = self;
144 amd64_transform_graph (cg);
147 dump_ir_graph(cg->irg, "transformed");
152 * Called immediatly before emit phase.
154 static void amd64_finish_irg(void *self)
156 amd64_code_gen_t *cg = self;
157 ir_graph *irg = cg->irg;
159 dump_ir_graph(irg, "amd64-finished");
162 static void amd64_before_ra(void *self)
164 amd64_code_gen_t *cg = self;
166 be_sched_fix_flags(cg->irg, &amd64_reg_classes[CLASS_amd64_flags], 0);
170 static void transform_Reload(ir_node *node)
172 ir_graph *irg = get_irn_irg(node);
173 ir_node *block = get_nodes_block(node);
174 dbg_info *dbgi = get_irn_dbg_info(node);
175 ir_node *ptr = get_irg_frame(irg);
176 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
177 ir_mode *mode = get_irn_mode(node);
178 ir_entity *entity = be_get_frame_entity(node);
179 const arch_register_t *reg;
183 ir_node *sched_point = sched_prev(node);
185 load = new_bd_amd64_Load(dbgi, block, ptr, mem, entity);
186 sched_add_after(sched_point, load);
189 proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
191 reg = arch_get_irn_register(node);
192 arch_set_irn_register(proj, reg);
194 exchange(node, proj);
197 static void transform_Spill(ir_node *node)
199 ir_graph *irg = get_irn_irg(node);
200 ir_node *block = get_nodes_block(node);
201 dbg_info *dbgi = get_irn_dbg_info(node);
202 ir_node *ptr = get_irg_frame(irg);
203 ir_node *mem = new_NoMem();
204 ir_node *val = get_irn_n(node, be_pos_Spill_val);
205 //ir_mode *mode = get_irn_mode(val);
206 ir_entity *entity = be_get_frame_entity(node);
207 ir_node *sched_point;
210 sched_point = sched_prev(node);
211 store = new_bd_amd64_Store(dbgi, block, ptr, val, mem, entity);
214 sched_add_after(sched_point, store);
216 exchange(node, store);
219 static void amd64_after_ra_walker(ir_node *block, void *data)
221 ir_node *node, *prev;
224 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
225 prev = sched_prev(node);
227 if (be_is_Reload(node)) {
228 transform_Reload(node);
229 } else if (be_is_Spill(node)) {
230 transform_Spill(node);
235 static void amd64_after_ra(void *self)
237 amd64_code_gen_t *cg = self;
238 be_coalesce_spillslots(cg->irg);
240 irg_block_walk_graph(cg->irg, NULL, amd64_after_ra_walker, NULL);
245 * Emits the code, closes the output file and frees
246 * the code generator interface.
248 static void amd64_emit_and_done(void *self)
250 amd64_code_gen_t *cg = self;
251 ir_graph *irg = cg->irg;
253 amd64_gen_routine(cg, irg);
255 /* de-allocate code generator */
259 static void *amd64_cg_init(ir_graph *irg);
261 static const arch_code_generator_if_t amd64_code_gen_if = {
263 NULL, /* get_pic_base hook */
264 NULL, /* before abi introduce hook */
266 NULL, /* spill hook */
267 amd64_before_ra, /* before register allocation hook */
268 amd64_after_ra, /* after register allocation hook */
274 * Initializes the code generator.
276 static void *amd64_cg_init(ir_graph *irg)
278 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
279 amd64_isa_t *isa = (amd64_isa_t *) arch_env;
280 amd64_code_gen_t *cg = XMALLOC(amd64_code_gen_t);
282 cg->impl = &amd64_code_gen_if;
285 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
287 return (arch_code_generator_t *)cg;
291 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
294 * Used to create per-graph unique pseudo nodes.
296 static inline ir_node *create_const(amd64_code_gen_t *cg, ir_node **place,
297 create_const_node_func func,
298 const arch_register_t* reg)
300 ir_node *block, *res;
305 block = get_irg_start_block(cg->irg);
306 res = func(NULL, block);
307 arch_set_irn_register(res, reg);
313 const arch_isa_if_t amd64_isa_if;
314 static amd64_isa_t amd64_isa_template = {
316 &amd64_isa_if, /* isa interface implementation */
317 &amd64_gp_regs[REG_RSP], /* stack pointer register */
318 &amd64_gp_regs[REG_RBP], /* base pointer register */
319 &amd64_reg_classes[CLASS_amd64_gp], /* link pointer register class */
320 -1, /* stack direction */
321 3, /* power of two stack alignment for calls, 2^2 == 4 */
322 NULL, /* main environment */
323 7, /* costs for a spill instruction */
324 5, /* costs for a reload instruction */
329 * Initializes the backend ISA
331 static arch_env_t *amd64_init(FILE *outfile)
333 static int run_once = 0;
340 isa = XMALLOC(amd64_isa_t);
341 memcpy(isa, &amd64_isa_template, sizeof(*isa));
343 be_emit_init(outfile);
345 amd64_register_init();
346 amd64_create_opcodes(&amd64_irn_ops);
348 return &isa->arch_env;
354 * Closes the output file and frees the ISA structure.
356 static void amd64_done(void *self)
358 amd64_isa_t *isa = self;
360 /* emit now all global declarations */
361 be_gas_emit_decls(isa->arch_env.main_env);
368 static unsigned amd64_get_n_reg_class(void)
373 static const arch_register_class_t *amd64_get_reg_class(unsigned i)
375 assert(i < N_CLASSES);
376 return &amd64_reg_classes[i];
382 * Get the register class which shall be used to store a value of a given mode.
383 * @param self The this pointer.
384 * @param mode The mode in question.
385 * @return A register class which can hold values of the given mode.
387 static const arch_register_class_t *amd64_get_reg_class_for_mode(const ir_mode *mode)
389 assert(!mode_is_float(mode));
390 return &amd64_reg_classes[CLASS_amd64_gp];
396 be_abi_call_flags_bits_t flags;
397 const arch_env_t *arch_env;
401 static void *amd64_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
403 amd64_abi_env_t *env = XMALLOC(amd64_abi_env_t);
404 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
405 env->flags = fl.bits;
407 env->arch_env = arch_env;
412 * Get the between type for that call.
413 * @param self The callback object.
414 * @return The between type of for that call.
416 static ir_type *amd64_get_between_type(void *self)
418 static ir_type *between_type = NULL;
419 static ir_entity *old_bp_ent = NULL;
423 ir_entity *ret_addr_ent;
424 ir_type *ret_addr_type = new_type_primitive(mode_P);
425 ir_type *old_bp_type = new_type_primitive(mode_P);
427 between_type = new_type_class(new_id_from_str("amd64_between_type"));
428 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
429 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
431 set_entity_offset(old_bp_ent, 0);
432 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
433 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
440 * Build the prolog, return the BASE POINTER register
442 static const arch_register_t *amd64_abi_prologue(void *self, ir_node **mem,
443 pmap *reg_map, int *stack_bias)
445 amd64_abi_env_t *env = self;
446 const arch_env_t *aenv = env->arch_env;
452 if (!env->flags.try_omit_fp) {
453 /* FIXME: maybe later here should be some code to generate
454 * the usual abi prologue */
455 return env->arch_env->bp;
458 return env->arch_env->sp;
461 /* Build the epilog */
462 static void amd64_abi_epilogue(void *self, ir_node *bl, ir_node **mem,
465 amd64_abi_env_t *env = self;
466 const arch_env_t *aenv = env->arch_env;
467 ir_node *curr_sp = be_abi_reg_map_get(reg_map, aenv->sp);
468 ir_node *curr_bp = be_abi_reg_map_get(reg_map, aenv->bp);
472 if (env->flags.try_omit_fp) {
473 curr_sp = be_new_IncSP(aenv->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
476 be_abi_reg_map_set(reg_map, aenv->sp, curr_sp);
477 be_abi_reg_map_set(reg_map, aenv->bp, curr_bp);
480 static const be_abi_callbacks_t amd64_abi_callbacks = {
483 amd64_get_between_type,
488 static const arch_register_t *gpreg_param_reg_std[] = {
489 &amd64_gp_regs[REG_RDI],
490 &amd64_gp_regs[REG_RSI],
491 &amd64_gp_regs[REG_RDX],
492 &amd64_gp_regs[REG_RCX],
493 &amd64_gp_regs[REG_R8],
494 &amd64_gp_regs[REG_R9],
497 static const arch_register_t *amd64_get_RegParam_reg(int n)
499 assert(n < 6 && n >=0 && "register param > 6 requested");
500 return gpreg_param_reg_std[n];
504 * Get the ABI restrictions for procedure calls.
505 * @param self The this pointer.
506 * @param method_type The type of the method (procedure) in question.
507 * @param abi The abi object to be modified
509 static void amd64_get_call_abi(const void *self, ir_type *method_type,
514 int i, n = get_method_n_params(method_type);
515 be_abi_call_flags_t call_flags;
520 /* set abi flags for calls */
521 call_flags.bits.left_to_right = 0;
522 call_flags.bits.store_args_sequential = 0;
523 call_flags.bits.try_omit_fp = 1;
524 call_flags.bits.fp_free = 0;
525 call_flags.bits.call_has_imm = 1;
527 /* set stack parameter passing style */
528 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
530 for (i = 0; i < n; i++) {
531 tp = get_method_param_type(method_type, i);
532 mode = get_type_mode(tp);
533 //d// printf ("MODE %p %p XX %d\n", mode, mode_Iu, i);
535 if (!no_reg && i < 6 && mode_is_data (mode)) {
536 //d// printf("TEST%d\n", i);
537 be_abi_call_param_reg(abi, i, amd64_get_RegParam_reg (i),
539 /* default: all parameters on stack */
542 be_abi_call_param_stack(abi, i, mode, 8, 0, 0, ABI_CONTEXT_BOTH);
546 /* TODO: set correct return register */
547 /* default: return value is in R0 resp. F0 */
548 if (get_method_n_ress(method_type) > 0) {
549 tp = get_method_res_type(method_type, 0);
550 mode = get_type_mode(tp);
552 /* FIXME: No floating point yet */
553 /* be_abi_call_res_reg(abi, 0,
554 mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_gp_regs[REG_R0], ABI_CONTEXT_BOTH) */;
556 be_abi_call_res_reg(abi, 0,
557 &amd64_gp_regs[REG_RAX], ABI_CONTEXT_BOTH);
561 static int amd64_to_appear_in_schedule(void *block_env, const ir_node *irn)
565 if(!is_amd64_irn(irn))
572 * Initializes the code generator interface.
574 static const arch_code_generator_if_t *amd64_get_code_generator_if(
578 return &amd64_code_gen_if;
581 list_sched_selector_t amd64_sched_selector;
584 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
586 static const list_sched_selector_t *amd64_get_list_sched_selector(
587 const void *self, list_sched_selector_t *selector)
592 amd64_sched_selector = trivial_selector;
593 amd64_sched_selector.to_appear_in_schedule = amd64_to_appear_in_schedule;
594 return &amd64_sched_selector;
597 static const ilp_sched_selector_t *amd64_get_ilp_sched_selector(
605 * Returns the necessary byte alignment for storing a register of given class.
607 static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
609 ir_mode *mode = arch_register_class_mode(cls);
610 return get_mode_size_bytes(mode);
614 * Returns the libFirm configuration parameter for this backend.
616 static const backend_params *amd64_get_backend_params(void) {
617 static backend_params p = {
618 0, /* no dword lowering */
619 0, /* no inline assembly */
620 NULL, /* will be set later */
621 NULL, /* no creator function */
622 NULL, /* context for create_intrinsic_fkt */
623 NULL, /* parameter for if conversion */
624 NULL, /* float arithmetic mode */
625 0, /* no trampoline support: size 0 */
626 0, /* no trampoline support: align 0 */
627 NULL, /* no trampoline support: no trampoline builder */
628 8 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
633 static const be_execution_unit_t ***amd64_get_allowed_execution_units(
642 static const be_machine_t *amd64_get_machine(const void *self)
650 static ir_graph **amd64_get_backend_irg_list(const void *self,
658 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
661 return ASM_CONSTRAINT_FLAG_INVALID;
664 static int amd64_is_valid_clobber(const char *clobber)
670 const arch_isa_if_t amd64_isa_if = {
673 NULL, /* handle intrinsics */
674 amd64_get_n_reg_class,
676 amd64_get_reg_class_for_mode,
678 amd64_get_code_generator_if,
679 amd64_get_list_sched_selector,
680 amd64_get_ilp_sched_selector,
681 amd64_get_reg_class_alignment,
682 amd64_get_backend_params,
683 amd64_get_allowed_execution_units,
685 amd64_get_backend_irg_list,
686 NULL, /* mark remat */
687 amd64_parse_asm_constraint,
688 amd64_is_valid_clobber
691 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64);
692 void be_init_arch_amd64(void)
694 be_register_isa_if("amd64", &amd64_isa_if);
695 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
696 amd64_init_transform();