2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
23 * @version $Id: bearch_amd64.c 26909 2010-01-05 15:56:54Z matze $
38 #include "../bearch.h"
39 #include "../benode.h"
40 #include "../belower.h"
41 #include "../besched.h"
43 #include "../bemodule.h"
44 #include "../begnuas.h"
45 #include "../belistsched.h"
46 #include "../beflags.h"
47 #include "../bespillslots.h"
49 #include "bearch_amd64_t.h"
51 #include "amd64_new_nodes.h"
52 #include "gen_amd64_regalloc_if.h"
53 #include "amd64_transform.h"
54 #include "amd64_emitter.h"
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 static arch_irn_class_t amd64_classify(const ir_node *irn)
64 static ir_entity *amd64_get_frame_entity(const ir_node *node)
66 if (is_amd64_FrameAddr(node)) {
67 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
70 } else if (is_amd64_Store(node)) {
71 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
74 } else if (is_amd64_Load(node)) {
75 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
80 /* TODO: return the ir_entity assigned to the frame */
85 * This function is called by the generic backend to correct offsets for
86 * nodes accessing the stack.
88 static void amd64_set_frame_offset(ir_node *irn, int offset)
90 if (is_amd64_FrameAddr(irn)) {
91 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
92 attr->fp_offset += offset;
94 } else if (is_amd64_Store(irn)) {
95 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
96 attr->fp_offset += offset;
98 } else if (is_amd64_Load(irn)) {
99 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
100 attr->fp_offset += offset;
105 static int amd64_get_sp_bias(const ir_node *irn)
111 /* fill register allocator interface */
113 static const arch_irn_ops_t amd64_irn_ops = {
115 amd64_get_frame_entity,
116 amd64_set_frame_offset,
118 NULL, /* get_inverse */
119 NULL, /* get_op_estimated_cost */
120 NULL, /* possible_memory_operand */
121 NULL, /* perform_memory_operand */
127 * Transforms the standard firm graph into
130 static void amd64_prepare_graph(ir_graph *irg)
132 amd64_irg_data_t *irg_data = amd64_get_irg_data(irg);
133 amd64_transform_graph(irg);
136 dump_ir_graph(irg, "transformed");
141 * Called immediatly before emit phase.
143 static void amd64_finish_irg(ir_graph *irg)
148 static void amd64_before_ra(ir_graph *irg)
150 be_sched_fix_flags(irg, &amd64_reg_classes[CLASS_amd64_flags], NULL, NULL);
154 static void transform_Reload(ir_node *node)
156 ir_graph *irg = get_irn_irg(node);
157 ir_node *block = get_nodes_block(node);
158 dbg_info *dbgi = get_irn_dbg_info(node);
159 ir_node *ptr = get_irg_frame(irg);
160 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
161 ir_mode *mode = get_irn_mode(node);
162 ir_entity *entity = be_get_frame_entity(node);
163 const arch_register_t *reg;
167 ir_node *sched_point = sched_prev(node);
169 load = new_bd_amd64_Load(dbgi, block, ptr, mem, entity);
170 sched_add_after(sched_point, load);
173 proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
175 reg = arch_get_irn_register(node);
176 arch_set_irn_register(proj, reg);
178 exchange(node, proj);
181 static void transform_Spill(ir_node *node)
183 ir_graph *irg = get_irn_irg(node);
184 ir_node *block = get_nodes_block(node);
185 dbg_info *dbgi = get_irn_dbg_info(node);
186 ir_node *ptr = get_irg_frame(irg);
187 ir_node *mem = new_r_NoMem(irg);
188 ir_node *val = get_irn_n(node, be_pos_Spill_val);
189 //ir_mode *mode = get_irn_mode(val);
190 ir_entity *entity = be_get_frame_entity(node);
191 ir_node *sched_point;
194 sched_point = sched_prev(node);
195 store = new_bd_amd64_Store(dbgi, block, ptr, val, mem, entity);
198 sched_add_after(sched_point, store);
200 exchange(node, store);
203 static void amd64_after_ra_walker(ir_node *block, void *data)
205 ir_node *node, *prev;
208 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
209 prev = sched_prev(node);
211 if (be_is_Reload(node)) {
212 transform_Reload(node);
213 } else if (be_is_Spill(node)) {
214 transform_Spill(node);
219 static void amd64_after_ra(ir_graph *irg)
221 be_coalesce_spillslots(irg);
223 irg_block_walk_graph(irg, NULL, amd64_after_ra_walker, NULL);
227 * Initializes the code generator.
229 static void amd64_init_graph(ir_graph *irg)
231 struct obstack *obst = be_get_be_obst(irg);
232 amd64_irg_data_t *irg_data = OALLOCZ(obst, amd64_irg_data_t);
233 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
235 be_birg_from_irg(irg)->isa_link = irg_data;
239 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
242 * Used to create per-graph unique pseudo nodes.
244 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
245 create_const_node_func func,
246 const arch_register_t* reg)
248 ir_node *block, *res;
253 block = get_irg_start_block(irg);
254 res = func(NULL, block);
255 arch_set_irn_register(res, reg);
261 const arch_isa_if_t amd64_isa_if;
262 static amd64_isa_t amd64_isa_template = {
264 &amd64_isa_if, /* isa interface implementation */
267 &amd64_registers[REG_RSP], /* stack pointer register */
268 &amd64_registers[REG_RBP], /* base pointer register */
269 &amd64_reg_classes[CLASS_amd64_gp], /* link pointer register class */
270 -1, /* stack direction */
271 3, /* power of two stack alignment for calls, 2^2 == 4 */
272 NULL, /* main environment */
273 7, /* costs for a spill instruction */
274 5, /* costs for a reload instruction */
275 false, /* no custom abi handling */
280 * Initializes the backend ISA
282 static arch_env_t *amd64_init(FILE *outfile)
284 static int run_once = 0;
291 isa = XMALLOC(amd64_isa_t);
292 memcpy(isa, &amd64_isa_template, sizeof(*isa));
294 be_emit_init(outfile);
296 amd64_register_init();
297 amd64_create_opcodes(&amd64_irn_ops);
305 * Closes the output file and frees the ISA structure.
307 static void amd64_done(void *self)
309 amd64_isa_t *isa = self;
311 /* emit now all global declarations */
312 be_gas_emit_decls(isa->base.main_env);
319 static unsigned amd64_get_n_reg_class(void)
321 return N_AMD64_CLASSES;
324 static const arch_register_class_t *amd64_get_reg_class(unsigned i)
326 assert(i < N_AMD64_CLASSES);
327 return &amd64_reg_classes[i];
333 * Get the register class which shall be used to store a value of a given mode.
334 * @param self The this pointer.
335 * @param mode The mode in question.
336 * @return A register class which can hold values of the given mode.
338 static const arch_register_class_t *amd64_get_reg_class_for_mode(const ir_mode *mode)
340 assert(!mode_is_float(mode));
341 return &amd64_reg_classes[CLASS_amd64_gp];
347 be_abi_call_flags_bits_t flags;
351 static void *amd64_abi_init(const be_abi_call_t *call, ir_graph *irg)
353 amd64_abi_env_t *env = XMALLOC(amd64_abi_env_t);
354 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
355 env->flags = fl.bits;
361 * Get the between type for that call.
362 * @param self The callback object.
363 * @return The between type of for that call.
365 static ir_type *amd64_get_between_type(void *self)
367 static ir_type *between_type = NULL;
368 static ir_entity *old_bp_ent = NULL;
372 ir_entity *ret_addr_ent;
373 ir_type *ret_addr_type = new_type_primitive(mode_P);
374 ir_type *old_bp_type = new_type_primitive(mode_P);
376 between_type = new_type_class(new_id_from_str("amd64_between_type"));
377 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
378 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
380 set_entity_offset(old_bp_ent, 0);
381 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
382 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
389 * Build the prolog, return the BASE POINTER register
391 static const arch_register_t *amd64_abi_prologue(void *self, ir_node **mem,
392 pmap *reg_map, int *stack_bias)
394 amd64_abi_env_t *env = self;
395 const arch_env_t *aenv = be_get_irg_arch_env(env->irg);
401 if (!env->flags.try_omit_fp) {
402 /* FIXME: maybe later here should be some code to generate
403 * the usual abi prologue */
410 /* Build the epilog */
411 static void amd64_abi_epilogue(void *self, ir_node *bl, ir_node **mem,
414 amd64_abi_env_t *env = self;
415 const arch_env_t *aenv = be_get_irg_arch_env(env->irg);
416 ir_node *curr_sp = be_abi_reg_map_get(reg_map, aenv->sp);
417 ir_node *curr_bp = be_abi_reg_map_get(reg_map, aenv->bp);
421 if (env->flags.try_omit_fp) {
422 curr_sp = be_new_IncSP(aenv->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
425 be_abi_reg_map_set(reg_map, aenv->sp, curr_sp);
426 be_abi_reg_map_set(reg_map, aenv->bp, curr_bp);
429 static const be_abi_callbacks_t amd64_abi_callbacks = {
432 amd64_get_between_type,
437 static const arch_register_t *gpreg_param_reg_std[] = {
438 &amd64_registers[REG_RDI],
439 &amd64_registers[REG_RSI],
440 &amd64_registers[REG_RDX],
441 &amd64_registers[REG_RCX],
442 &amd64_registers[REG_R8],
443 &amd64_registers[REG_R9],
446 static const arch_register_t *amd64_get_RegParam_reg(int n)
448 assert(n < 6 && n >=0 && "register param > 6 requested");
449 return gpreg_param_reg_std[n];
453 * Get the ABI restrictions for procedure calls.
454 * @param self The this pointer.
455 * @param method_type The type of the method (procedure) in question.
456 * @param abi The abi object to be modified
458 static void amd64_get_call_abi(const void *self, ir_type *method_type,
463 int i, n = get_method_n_params(method_type);
464 be_abi_call_flags_t call_flags;
469 /* set abi flags for calls */
470 call_flags.bits.left_to_right = 0;
471 call_flags.bits.store_args_sequential = 0;
472 call_flags.bits.try_omit_fp = 1;
473 call_flags.bits.fp_free = 0;
474 call_flags.bits.call_has_imm = 1;
476 /* set stack parameter passing style */
477 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
479 for (i = 0; i < n; i++) {
480 tp = get_method_param_type(method_type, i);
481 mode = get_type_mode(tp);
482 //d// printf ("MODE %p %p XX %d\n", mode, mode_Iu, i);
484 if (!no_reg && i < 6 && mode_is_data (mode)) {
485 //d// printf("TEST%d\n", i);
486 be_abi_call_param_reg(abi, i, amd64_get_RegParam_reg (i),
488 /* default: all parameters on stack */
491 be_abi_call_param_stack(abi, i, mode, 8, 0, 0, ABI_CONTEXT_BOTH);
495 /* TODO: set correct return register */
496 /* default: return value is in R0 resp. F0 */
497 if (get_method_n_ress(method_type) > 0) {
498 tp = get_method_res_type(method_type, 0);
499 mode = get_type_mode(tp);
501 /* FIXME: No floating point yet */
502 /* be_abi_call_res_reg(abi, 0,
503 mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_registers[REG_R0], ABI_CONTEXT_BOTH) */;
505 be_abi_call_res_reg(abi, 0,
506 &amd64_registers[REG_RAX], ABI_CONTEXT_BOTH);
511 * Returns the necessary byte alignment for storing a register of given class.
513 static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
515 ir_mode *mode = arch_register_class_mode(cls);
516 return get_mode_size_bytes(mode);
519 static void amd64_lower_for_target(void)
523 static int amd64_is_mux_allowed(ir_node *sel, ir_node *mux_false,
533 * Returns the libFirm configuration parameter for this backend.
535 static const backend_params *amd64_get_backend_params(void) {
536 static backend_params p = {
537 0, /* no inline assembly */
538 1, /* support Rotl nodes */
539 0, /* little endian */
540 amd64_lower_for_target, /* lowering callback */
541 NULL, /* will be set later */
542 amd64_is_mux_allowed, /* parameter for if conversion */
543 NULL, /* float arithmetic mode */
544 0, /* no trampoline support: size 0 */
545 0, /* no trampoline support: align 0 */
546 NULL, /* no trampoline support: no trampoline builder */
547 8 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
552 static ir_graph **amd64_get_backend_irg_list(const void *self,
560 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
563 return ASM_CONSTRAINT_FLAG_INVALID;
566 static int amd64_is_valid_clobber(const char *clobber)
572 const arch_isa_if_t amd64_isa_if = {
575 NULL, /* handle intrinsics */
576 amd64_get_n_reg_class,
578 amd64_get_reg_class_for_mode,
580 amd64_get_reg_class_alignment,
581 amd64_get_backend_params,
582 amd64_get_backend_irg_list,
583 NULL, /* mark remat */
584 amd64_parse_asm_constraint,
585 amd64_is_valid_clobber,
588 NULL, /* get_pic_base */
589 NULL, /* before_abi */
597 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64);
598 void be_init_arch_amd64(void)
600 be_register_isa_if("amd64", &amd64_isa_if);
601 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
602 amd64_init_transform();