2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
32 #include "lower_calls.h"
47 #include "belistsched.h"
49 #include "bespillslots.h"
50 #include "bespillutil.h"
53 #include "bearch_amd64_t.h"
55 #include "amd64_new_nodes.h"
56 #include "gen_amd64_regalloc_if.h"
57 #include "amd64_transform.h"
58 #include "amd64_emitter.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 static ir_entity *amd64_get_frame_entity(const ir_node *node)
64 if (is_amd64_FrameAddr(node)) {
65 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
68 } else if (is_amd64_Store(node)) {
69 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
72 } else if (is_amd64_Load(node)) {
73 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
78 /* TODO: return the ir_entity assigned to the frame */
83 * This function is called by the generic backend to correct offsets for
84 * nodes accessing the stack.
86 static void amd64_set_frame_offset(ir_node *irn, int offset)
88 if (is_amd64_FrameAddr(irn)) {
89 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
90 attr->fp_offset += offset;
92 } else if (is_amd64_Store(irn)) {
93 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
94 attr->fp_offset += offset;
96 } else if (is_amd64_Load(irn)) {
97 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
98 attr->fp_offset += offset;
103 static int amd64_get_sp_bias(const ir_node *irn)
109 /* fill register allocator interface */
111 static const arch_irn_ops_t amd64_irn_ops = {
112 amd64_get_frame_entity,
113 amd64_set_frame_offset,
115 NULL, /* get_op_estimated_cost */
116 NULL, /* possible_memory_operand */
117 NULL, /* perform_memory_operand */
123 * Transforms the standard firm graph into
126 static void amd64_prepare_graph(ir_graph *irg)
128 amd64_transform_graph(irg);
130 if (be_options.dump_flags & DUMP_BE)
131 dump_ir_graph(irg, "transformed");
134 static void amd64_before_ra(ir_graph *irg)
136 be_sched_fix_flags(irg, &amd64_reg_classes[CLASS_amd64_flags], NULL, NULL);
139 static void transform_Reload(ir_node *node)
141 ir_graph *irg = get_irn_irg(node);
142 ir_node *block = get_nodes_block(node);
143 dbg_info *dbgi = get_irn_dbg_info(node);
144 ir_node *ptr = get_irg_frame(irg);
145 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
146 ir_mode *mode = get_irn_mode(node);
147 ir_entity *entity = be_get_frame_entity(node);
148 const arch_register_t *reg;
152 ir_node *sched_point = sched_prev(node);
154 load = new_bd_amd64_Load(dbgi, block, ptr, mem, entity);
155 sched_add_after(sched_point, load);
158 proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
160 reg = arch_get_irn_register(node);
161 arch_set_irn_register(proj, reg);
163 exchange(node, proj);
166 static void transform_Spill(ir_node *node)
168 ir_graph *irg = get_irn_irg(node);
169 ir_node *block = get_nodes_block(node);
170 dbg_info *dbgi = get_irn_dbg_info(node);
171 ir_node *ptr = get_irg_frame(irg);
172 ir_node *mem = get_irg_no_mem(irg);
173 ir_node *val = get_irn_n(node, n_be_Spill_val);
174 //ir_mode *mode = get_irn_mode(val);
175 ir_entity *entity = be_get_frame_entity(node);
176 ir_node *sched_point;
179 sched_point = sched_prev(node);
180 store = new_bd_amd64_Store(dbgi, block, ptr, val, mem, entity);
183 sched_add_after(sched_point, store);
185 exchange(node, store);
188 static void amd64_after_ra_walker(ir_node *block, void *data)
190 ir_node *node, *prev;
193 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
194 prev = sched_prev(node);
196 if (be_is_Reload(node)) {
197 transform_Reload(node);
198 } else if (be_is_Spill(node)) {
199 transform_Spill(node);
204 static void amd64_set_frame_entity(ir_node *node, ir_entity *entity)
206 assert(be_is_Reload(node) || be_is_Spill(node));
207 be_node_set_frame_entity(node, entity);
211 * Collects nodes that need frame entities assigned.
213 static void amd64_collect_frame_entity_nodes(ir_node *node, void *data)
215 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
216 be_fec_env_t *env = (be_fec_env_t*)data;
217 const ir_mode *mode = get_irn_mode(node);
218 int align = get_mode_size_bytes(mode);
219 be_node_needs_frame_entity(env, node, mode, align);
224 * Called immediatly before emit phase.
226 static void amd64_finish_irg(ir_graph *irg)
228 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
229 bool at_begin = stack_layout->sp_relative ? true : false;
230 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
232 /* create and coalesce frame entities */
233 irg_walk_graph(irg, NULL, amd64_collect_frame_entity_nodes, fec_env);
234 be_assign_entities(fec_env, amd64_set_frame_entity, at_begin);
235 be_free_frame_entity_coalescer(fec_env);
237 irg_block_walk_graph(irg, NULL, amd64_after_ra_walker, NULL);
239 /* fix stack entity offsets */
240 be_abi_fix_stack_nodes(irg);
241 be_abi_fix_stack_bias(irg);
244 extern const arch_isa_if_t amd64_isa_if;
245 static amd64_isa_t amd64_isa_template = {
247 &amd64_isa_if, /* isa interface implementation */
252 &amd64_registers[REG_RSP], /* stack pointer register */
253 &amd64_registers[REG_RBP], /* base pointer register */
254 3, /* power of two stack alignment for calls, 2^2 == 4 */
255 NULL, /* main environment */
256 7, /* costs for a spill instruction */
257 5, /* costs for a reload instruction */
258 false, /* no custom abi handling */
262 static void amd64_init(void)
264 amd64_register_init();
265 amd64_create_opcodes(&amd64_irn_ops);
268 static void amd64_finish(void)
270 amd64_free_opcodes();
273 static arch_env_t *amd64_begin_codegeneration(void)
275 amd64_isa_t *isa = XMALLOC(amd64_isa_t);
276 *isa = amd64_isa_template;
282 * Closes the output file and frees the ISA structure.
284 static void amd64_end_codegeneration(void *self)
286 amd64_isa_t *isa = (amd64_isa_t*)self;
288 /* emit now all global declarations */
289 be_gas_end_compilation_unit(isa->base.main_env);
296 * Get the between type for that call.
297 * @param self The callback object.
298 * @return The between type of for that call.
300 static ir_type *amd64_get_between_type(ir_graph *irg)
302 static ir_type *between_type = NULL;
303 static ir_entity *old_bp_ent = NULL;
307 ir_entity *ret_addr_ent;
308 ir_type *ret_addr_type = new_type_primitive(mode_P);
309 ir_type *old_bp_type = new_type_primitive(mode_P);
311 between_type = new_type_class(new_id_from_str("amd64_between_type"));
312 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
313 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
315 set_entity_offset(old_bp_ent, 0);
316 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
317 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
323 static const be_abi_callbacks_t amd64_abi_callbacks = {
324 amd64_get_between_type,
327 static const arch_register_t *gpreg_param_reg_std[] = {
328 &amd64_registers[REG_RDI],
329 &amd64_registers[REG_RSI],
330 &amd64_registers[REG_RDX],
331 &amd64_registers[REG_RCX],
332 &amd64_registers[REG_R8],
333 &amd64_registers[REG_R9],
336 static const arch_register_t *amd64_get_RegParam_reg(int n)
338 assert(n < 6 && n >=0 && "register param > 6 requested");
339 return gpreg_param_reg_std[n];
343 * Get the ABI restrictions for procedure calls.
344 * @param self The this pointer.
345 * @param method_type The type of the method (procedure) in question.
346 * @param abi The abi object to be modified
348 static void amd64_get_call_abi(ir_type *method_type, be_abi_call_t *abi)
352 int i, n = get_method_n_params(method_type);
355 /* set abi flags for calls */
356 be_abi_call_flags_t call_flags = be_abi_call_get_flags(abi);
357 call_flags.call_has_imm = true;
358 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
360 for (i = 0; i < n; i++) {
361 tp = get_method_param_type(method_type, i);
362 mode = get_type_mode(tp);
363 //d// printf ("MODE %p %p XX %d\n", mode, mode_Iu, i);
365 if (!no_reg && i < 6 && mode_is_data (mode)) {
366 //d// printf("TEST%d\n", i);
367 be_abi_call_param_reg(abi, i, amd64_get_RegParam_reg (i),
369 /* default: all parameters on stack */
372 be_abi_call_param_stack(abi, i, mode, 8, 0, 0, ABI_CONTEXT_BOTH);
376 /* TODO: set correct return register */
377 /* default: return value is in R0 resp. F0 */
378 if (get_method_n_ress(method_type) > 0) {
379 tp = get_method_res_type(method_type, 0);
380 mode = get_type_mode(tp);
382 if (mode_is_float(mode))
383 panic("float not supported yet");
385 be_abi_call_res_reg(abi, 0,
386 &amd64_registers[REG_RAX], ABI_CONTEXT_BOTH);
390 static void amd64_lower_for_target(void)
392 size_t i, n_irgs = get_irp_n_irgs();
394 /* lower compound param handling */
395 lower_calls_with_compounds(LF_RETURN_HIDDEN);
397 for (i = 0; i < n_irgs; ++i) {
398 ir_graph *irg = get_irp_irg(i);
399 /* Turn all small CopyBs into loads/stores, and turn all bigger
400 * CopyBs into memcpy calls, because we cannot handle CopyB nodes
401 * during code generation yet.
402 * TODO: Adapt this once custom CopyB handling is implemented. */
403 lower_CopyB(irg, 64, 65, true);
407 static int amd64_is_mux_allowed(ir_node *sel, ir_node *mux_false,
417 * Returns the libFirm configuration parameter for this backend.
419 static const backend_params *amd64_get_backend_params(void) {
420 static backend_params p = {
421 0, /* no inline assembly */
422 1, /* support Rotl nodes */
423 0, /* little endian */
424 1, /* modulo shift is efficient */
425 0, /* non-modulo shift is not efficient */
426 NULL, /* will be set later */
427 amd64_is_mux_allowed, /* parameter for if conversion */
428 64, /* machine size */
429 NULL, /* float arithmetic mode */
430 NULL, /* long long type */
431 NULL, /* unsigned long long type */
432 NULL, /* long double type (not supported yet) */
433 0, /* no trampoline support: size 0 */
434 0, /* no trampoline support: align 0 */
435 NULL, /* no trampoline support: no trampoline builder */
436 8 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
441 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
444 return ASM_CONSTRAINT_FLAG_INVALID;
447 static int amd64_is_valid_clobber(const char *clobber)
453 static int amd64_register_saved_by(const arch_register_t *reg, int callee)
456 /* check for callee saved */
457 if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_gp]) {
458 switch (reg->index) {
471 /* check for caller saved */
472 if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_gp]) {
473 switch (reg->index) {
492 const arch_isa_if_t amd64_isa_if = {
495 amd64_get_backend_params,
496 amd64_lower_for_target,
497 amd64_parse_asm_constraint,
498 amd64_is_valid_clobber,
500 amd64_begin_codegeneration,
501 amd64_end_codegeneration,
504 NULL, /* mark remat */
505 NULL, /* get_pic_base */
508 amd64_register_saved_by,
510 NULL, /* handle intrinsics */
511 NULL, /* before_abi */
518 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64)
519 void be_init_arch_amd64(void)
521 be_register_isa_if("amd64", &amd64_isa_if);
522 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
523 amd64_init_transform();