2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
23 * @version $Id: bearch_amd64.c 26909 2010-01-05 15:56:54Z matze $
27 #include "pseudo_irg.h"
39 #include "../bearch.h"
40 #include "../benode.h"
41 #include "../belower.h"
42 #include "../besched.h"
44 #include "../bemodule.h"
45 #include "../begnuas.h"
46 #include "../belistsched.h"
47 #include "../beflags.h"
48 #include "../bespillslots.h"
50 #include "bearch_amd64_t.h"
52 #include "amd64_new_nodes.h"
53 #include "gen_amd64_regalloc_if.h"
54 #include "amd64_transform.h"
55 #include "amd64_emitter.h"
57 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
59 static arch_irn_class_t amd64_classify(const ir_node *irn)
65 static ir_entity *amd64_get_frame_entity(const ir_node *node)
67 if (is_amd64_FrameAddr(node)) {
68 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
73 /* TODO: return the ir_entity assigned to the frame */
77 static void amd64_set_frame_entity(ir_node *node, ir_entity *ent)
81 /* TODO: set the ir_entity assigned to the frame */
85 * This function is called by the generic backend to correct offsets for
86 * nodes accessing the stack.
88 static void amd64_set_frame_offset(ir_node *irn, int offset)
90 if (is_amd64_FrameAddr(irn)) {
91 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
92 attr->fp_offset += offset;
96 static int amd64_get_sp_bias(const ir_node *irn)
102 /* fill register allocator interface */
104 static const arch_irn_ops_t amd64_irn_ops = {
107 amd64_get_frame_entity,
108 amd64_set_frame_entity,
109 amd64_set_frame_offset,
111 NULL, /* get_inverse */
112 NULL, /* get_op_estimated_cost */
113 NULL, /* possible_memory_operand */
114 NULL, /* perform_memory_operand */
120 * Transforms the standard firm graph into
123 static void amd64_prepare_graph(void *self)
125 amd64_code_gen_t *cg = self;
127 amd64_transform_graph (cg);
130 dump_ir_graph(cg->irg, "transformed");
135 * Called immediatly before emit phase.
137 static void amd64_finish_irg(void *self)
139 amd64_code_gen_t *cg = self;
140 ir_graph *irg = cg->irg;
142 dump_ir_graph(irg, "amd64-finished");
145 static void amd64_before_ra(void *self)
147 amd64_code_gen_t *cg = self;
149 be_sched_fix_flags(cg->birg, &amd64_reg_classes[CLASS_amd64_flags], 0);
153 static void transform_Reload(ir_node *node)
155 ir_graph *irg = get_irn_irg(node);
156 ir_node *block = get_nodes_block(node);
157 dbg_info *dbgi = get_irn_dbg_info(node);
158 ir_node *ptr = get_irg_frame(irg);
159 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
160 ir_mode *mode = get_irn_mode(node);
161 //ir_entity *entity = be_get_frame_entity(node);
162 const arch_register_t *reg;
166 ir_node *sched_point = sched_prev(node);
168 load = new_bd_amd64_Load(dbgi, block, ptr, mem);
169 sched_add_after(sched_point, load);
172 proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
174 reg = arch_get_irn_register(node);
175 arch_set_irn_register(proj, reg);
177 exchange(node, proj);
180 static void transform_Spill(ir_node *node)
182 ir_graph *irg = get_irn_irg(node);
183 ir_node *block = get_nodes_block(node);
184 dbg_info *dbgi = get_irn_dbg_info(node);
185 ir_node *ptr = get_irg_frame(irg);
186 ir_node *mem = new_NoMem();
187 ir_node *val = get_irn_n(node, be_pos_Spill_val);
188 //ir_mode *mode = get_irn_mode(val);
189 //ir_entity *entity = be_get_frame_entity(node);
190 ir_node *sched_point;
193 sched_point = sched_prev(node);
194 store = new_bd_amd64_Store(dbgi, block, ptr, val, mem);
197 sched_add_after(sched_point, store);
199 exchange(node, store);
202 static void amd64_after_ra_walker(ir_node *block, void *data)
204 ir_node *node, *prev;
207 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
208 prev = sched_prev(node);
210 if (be_is_Reload(node)) {
211 transform_Reload(node);
212 } else if (be_is_Spill(node)) {
213 transform_Spill(node);
218 static void amd64_after_ra(void *self)
220 amd64_code_gen_t *cg = self;
221 be_coalesce_spillslots(cg->birg);
223 irg_block_walk_graph(cg->irg, NULL, amd64_after_ra_walker, NULL);
228 * Emits the code, closes the output file and frees
229 * the code generator interface.
231 static void amd64_emit_and_done(void *self)
233 amd64_code_gen_t *cg = self;
234 ir_graph *irg = cg->irg;
236 amd64_gen_routine(cg, irg);
238 /* de-allocate code generator */
242 static void *amd64_cg_init(be_irg_t *birg);
244 static const arch_code_generator_if_t amd64_code_gen_if = {
246 NULL, /* get_pic_base hook */
247 NULL, /* before abi introduce hook */
249 NULL, /* spill hook */
250 amd64_before_ra, /* before register allocation hook */
251 amd64_after_ra, /* after register allocation hook */
257 * Initializes the code generator.
259 static void *amd64_cg_init(be_irg_t *birg)
261 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
262 amd64_isa_t *isa = (amd64_isa_t *) arch_env;
263 amd64_code_gen_t *cg = XMALLOC(amd64_code_gen_t);
265 cg->impl = &amd64_code_gen_if;
266 cg->irg = be_get_birg_irg(birg);
269 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
271 return (arch_code_generator_t *)cg;
275 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
278 * Used to create per-graph unique pseudo nodes.
280 static inline ir_node *create_const(amd64_code_gen_t *cg, ir_node **place,
281 create_const_node_func func,
282 const arch_register_t* reg)
284 ir_node *block, *res;
289 block = get_irg_start_block(cg->irg);
290 res = func(NULL, block);
291 arch_set_irn_register(res, reg);
297 const arch_isa_if_t amd64_isa_if;
298 static amd64_isa_t amd64_isa_template = {
300 &amd64_isa_if, /* isa interface implementation */
301 &amd64_gp_regs[REG_RSP], /* stack pointer register */
302 &amd64_gp_regs[REG_RBP], /* base pointer register */
303 &amd64_reg_classes[CLASS_amd64_gp], /* link pointer register class */
304 -1, /* stack direction */
305 3, /* power of two stack alignment for calls, 2^2 == 4 */
306 NULL, /* main environment */
307 7, /* costs for a spill instruction */
308 5, /* costs for a reload instruction */
313 * Initializes the backend ISA
315 static arch_env_t *amd64_init(FILE *outfile)
317 static int run_once = 0;
324 isa = XMALLOC(amd64_isa_t);
325 memcpy(isa, &amd64_isa_template, sizeof(*isa));
327 be_emit_init(outfile);
329 amd64_register_init();
330 amd64_create_opcodes(&amd64_irn_ops);
332 return &isa->arch_env;
338 * Closes the output file and frees the ISA structure.
340 static void amd64_done(void *self)
342 amd64_isa_t *isa = self;
344 /* emit now all global declarations */
345 be_gas_emit_decls(isa->arch_env.main_env);
352 static unsigned amd64_get_n_reg_class(void)
357 static const arch_register_class_t *amd64_get_reg_class(unsigned i)
359 assert(i < N_CLASSES);
360 return &amd64_reg_classes[i];
366 * Get the register class which shall be used to store a value of a given mode.
367 * @param self The this pointer.
368 * @param mode The mode in question.
369 * @return A register class which can hold values of the given mode.
371 static const arch_register_class_t *amd64_get_reg_class_for_mode(const ir_mode *mode)
373 assert(!mode_is_float(mode));
374 return &amd64_reg_classes[CLASS_amd64_gp];
380 be_abi_call_flags_bits_t flags;
381 const arch_env_t *arch_env;
385 static void *amd64_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
387 amd64_abi_env_t *env = XMALLOC(amd64_abi_env_t);
388 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
389 env->flags = fl.bits;
391 env->arch_env = arch_env;
396 * Get the between type for that call.
397 * @param self The callback object.
398 * @return The between type of for that call.
400 static ir_type *amd64_get_between_type(void *self)
402 static ir_type *between_type = NULL;
403 static ir_entity *old_bp_ent = NULL;
407 ir_entity *ret_addr_ent;
408 ir_type *ret_addr_type = new_type_primitive(mode_P);
409 ir_type *old_bp_type = new_type_primitive(mode_P);
411 between_type = new_type_class(new_id_from_str("amd64_between_type"));
412 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
413 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
415 set_entity_offset(old_bp_ent, 0);
416 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
417 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
424 * Build the prolog, return the BASE POINTER register
426 static const arch_register_t *amd64_abi_prologue(void *self, ir_node **mem,
427 pmap *reg_map, int *stack_bias)
429 amd64_abi_env_t *env = self;
430 const arch_env_t *aenv = env->arch_env;
436 if (!env->flags.try_omit_fp) {
437 /* FIXME: maybe later here should be some code to generate
438 * the usual abi prologue */
439 return env->arch_env->bp;
442 return env->arch_env->sp;
445 /* Build the epilog */
446 static void amd64_abi_epilogue(void *self, ir_node *bl, ir_node **mem,
449 amd64_abi_env_t *env = self;
450 const arch_env_t *aenv = env->arch_env;
451 ir_node *curr_sp = be_abi_reg_map_get(reg_map, aenv->sp);
452 ir_node *curr_bp = be_abi_reg_map_get(reg_map, aenv->bp);
456 if (env->flags.try_omit_fp) {
457 curr_sp = be_new_IncSP(aenv->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
460 be_abi_reg_map_set(reg_map, aenv->sp, curr_sp);
461 be_abi_reg_map_set(reg_map, aenv->bp, curr_bp);
464 static const be_abi_callbacks_t amd64_abi_callbacks = {
467 amd64_get_between_type,
472 static const arch_register_t *gpreg_param_reg_std[] = {
473 &amd64_gp_regs[REG_RDI],
474 &amd64_gp_regs[REG_RSI],
475 &amd64_gp_regs[REG_RDX],
476 &amd64_gp_regs[REG_RCX],
477 &amd64_gp_regs[REG_R8],
478 &amd64_gp_regs[REG_R9],
481 static const arch_register_t *amd64_get_RegParam_reg(int n)
483 assert(n < 6 && n >=0 && "register param > 6 requested");
484 return gpreg_param_reg_std[n];
488 * Get the ABI restrictions for procedure calls.
489 * @param self The this pointer.
490 * @param method_type The type of the method (procedure) in question.
491 * @param abi The abi object to be modified
493 static void amd64_get_call_abi(const void *self, ir_type *method_type,
498 int i, n = get_method_n_params(method_type);
499 be_abi_call_flags_t call_flags;
504 /* set abi flags for calls */
505 call_flags.bits.left_to_right = 0;
506 call_flags.bits.store_args_sequential = 0;
507 call_flags.bits.try_omit_fp = 1;
508 call_flags.bits.fp_free = 0;
509 call_flags.bits.call_has_imm = 1;
511 /* set stack parameter passing style */
512 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
514 for (i = 0; i < n; i++) {
515 tp = get_method_param_type(method_type, i);
516 mode = get_type_mode(tp);
517 //d// printf ("MODE %p %p XX %d\n", mode, mode_Iu, i);
519 if (!no_reg && i < 6 && mode_is_data (mode)) {
520 //d// printf("TEST%d\n", i);
521 be_abi_call_param_reg(abi, i, amd64_get_RegParam_reg (i),
523 /* default: all parameters on stack */
526 be_abi_call_param_stack(abi, i, mode, 8, 0, 0, ABI_CONTEXT_BOTH);
530 /* TODO: set correct return register */
531 /* default: return value is in R0 resp. F0 */
532 if (get_method_n_ress(method_type) > 0) {
533 tp = get_method_res_type(method_type, 0);
534 mode = get_type_mode(tp);
536 /* FIXME: No floating point yet */
537 /* be_abi_call_res_reg(abi, 0,
538 mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_gp_regs[REG_R0], ABI_CONTEXT_BOTH) */;
540 be_abi_call_res_reg(abi, 0,
541 &amd64_gp_regs[REG_RAX], ABI_CONTEXT_BOTH);
545 static int amd64_to_appear_in_schedule(void *block_env, const ir_node *irn)
549 if(!is_amd64_irn(irn))
556 * Initializes the code generator interface.
558 static const arch_code_generator_if_t *amd64_get_code_generator_if(
562 return &amd64_code_gen_if;
565 list_sched_selector_t amd64_sched_selector;
568 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
570 static const list_sched_selector_t *amd64_get_list_sched_selector(
571 const void *self, list_sched_selector_t *selector)
576 amd64_sched_selector = trivial_selector;
577 amd64_sched_selector.to_appear_in_schedule = amd64_to_appear_in_schedule;
578 return &amd64_sched_selector;
581 static const ilp_sched_selector_t *amd64_get_ilp_sched_selector(
589 * Returns the necessary byte alignment for storing a register of given class.
591 static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
593 ir_mode *mode = arch_register_class_mode(cls);
594 return get_mode_size_bytes(mode);
598 * Returns the libFirm configuration parameter for this backend.
600 static const backend_params *amd64_get_backend_params(void) {
601 static backend_params p = {
602 0, /* no dword lowering */
603 0, /* no inline assembly */
604 NULL, /* will be set later */
605 NULL, /* no creator function */
606 NULL, /* context for create_intrinsic_fkt */
607 NULL, /* parameter for if conversion */
608 NULL, /* float arithmetic mode */
609 0, /* no trampoline support: size 0 */
610 0, /* no trampoline support: align 0 */
611 NULL, /* no trampoline support: no trampoline builder */
612 8 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
617 static const be_execution_unit_t ***amd64_get_allowed_execution_units(
626 static const be_machine_t *amd64_get_machine(const void *self)
634 static ir_graph **amd64_get_backend_irg_list(const void *self,
642 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
645 return ASM_CONSTRAINT_FLAG_INVALID;
648 static int amd64_is_valid_clobber(const char *clobber)
654 const arch_isa_if_t amd64_isa_if = {
657 NULL, /* handle intrinsics */
658 amd64_get_n_reg_class,
660 amd64_get_reg_class_for_mode,
662 amd64_get_code_generator_if,
663 amd64_get_list_sched_selector,
664 amd64_get_ilp_sched_selector,
665 amd64_get_reg_class_alignment,
666 amd64_get_backend_params,
667 amd64_get_allowed_execution_units,
669 amd64_get_backend_irg_list,
670 NULL, /* mark remat */
671 amd64_parse_asm_constraint,
672 amd64_is_valid_clobber
675 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64);
676 void be_init_arch_amd64(void)
678 be_register_isa_if("amd64", &amd64_isa_if);
679 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
680 amd64_init_transform();