2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
23 * @version $Id: bearch_amd64.c 26909 2010-01-05 15:56:54Z matze $
33 #include "lower_calls.h"
39 #include "../bearch.h"
40 #include "../benode.h"
41 #include "../belower.h"
42 #include "../besched.h"
44 #include "../bemodule.h"
45 #include "../begnuas.h"
46 #include "../belistsched.h"
47 #include "../beflags.h"
48 #include "../bespillslots.h"
49 #include "../bestack.h"
51 #include "bearch_amd64_t.h"
53 #include "amd64_new_nodes.h"
54 #include "gen_amd64_regalloc_if.h"
55 #include "amd64_transform.h"
56 #include "amd64_emitter.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static arch_irn_class_t amd64_classify(const ir_node *irn)
63 return arch_irn_class_none;
66 static ir_entity *amd64_get_frame_entity(const ir_node *node)
68 if (is_amd64_FrameAddr(node)) {
69 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
72 } else if (is_amd64_Store(node)) {
73 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
76 } else if (is_amd64_Load(node)) {
77 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
82 /* TODO: return the ir_entity assigned to the frame */
87 * This function is called by the generic backend to correct offsets for
88 * nodes accessing the stack.
90 static void amd64_set_frame_offset(ir_node *irn, int offset)
92 if (is_amd64_FrameAddr(irn)) {
93 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
94 attr->fp_offset += offset;
96 } else if (is_amd64_Store(irn)) {
97 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
98 attr->fp_offset += offset;
100 } else if (is_amd64_Load(irn)) {
101 amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr(irn);
102 attr->fp_offset += offset;
107 static int amd64_get_sp_bias(const ir_node *irn)
113 /* fill register allocator interface */
115 static const arch_irn_ops_t amd64_irn_ops = {
117 amd64_get_frame_entity,
118 amd64_set_frame_offset,
120 NULL, /* get_inverse */
121 NULL, /* get_op_estimated_cost */
122 NULL, /* possible_memory_operand */
123 NULL, /* perform_memory_operand */
129 * Transforms the standard firm graph into
132 static void amd64_prepare_graph(ir_graph *irg)
134 amd64_irg_data_t *irg_data = amd64_get_irg_data(irg);
135 amd64_transform_graph(irg);
138 dump_ir_graph(irg, "transformed");
141 static void amd64_before_ra(ir_graph *irg)
143 be_sched_fix_flags(irg, &amd64_reg_classes[CLASS_amd64_flags], NULL, NULL);
146 static void transform_Reload(ir_node *node)
148 ir_graph *irg = get_irn_irg(node);
149 ir_node *block = get_nodes_block(node);
150 dbg_info *dbgi = get_irn_dbg_info(node);
151 ir_node *ptr = get_irg_frame(irg);
152 ir_node *mem = get_irn_n(node, n_be_Reload_mem);
153 ir_mode *mode = get_irn_mode(node);
154 ir_entity *entity = be_get_frame_entity(node);
155 const arch_register_t *reg;
159 ir_node *sched_point = sched_prev(node);
161 load = new_bd_amd64_Load(dbgi, block, ptr, mem, entity);
162 sched_add_after(sched_point, load);
165 proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
167 reg = arch_get_irn_register(node);
168 arch_set_irn_register(proj, reg);
170 exchange(node, proj);
173 static void transform_Spill(ir_node *node)
175 ir_graph *irg = get_irn_irg(node);
176 ir_node *block = get_nodes_block(node);
177 dbg_info *dbgi = get_irn_dbg_info(node);
178 ir_node *ptr = get_irg_frame(irg);
179 ir_node *mem = get_irg_no_mem(irg);
180 ir_node *val = get_irn_n(node, n_be_Spill_val);
181 //ir_mode *mode = get_irn_mode(val);
182 ir_entity *entity = be_get_frame_entity(node);
183 ir_node *sched_point;
186 sched_point = sched_prev(node);
187 store = new_bd_amd64_Store(dbgi, block, ptr, val, mem, entity);
190 sched_add_after(sched_point, store);
192 exchange(node, store);
195 static void amd64_after_ra_walker(ir_node *block, void *data)
197 ir_node *node, *prev;
200 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
201 prev = sched_prev(node);
203 if (be_is_Reload(node)) {
204 transform_Reload(node);
205 } else if (be_is_Spill(node)) {
206 transform_Spill(node);
211 static void amd64_set_frame_entity(ir_node *node, ir_entity *entity)
213 assert(be_is_Reload(node));
214 be_node_set_frame_entity(node, entity);
218 * Collects nodes that need frame entities assigned.
220 static void amd64_collect_frame_entity_nodes(ir_node *node, void *data)
222 if (be_is_Reload(node) && be_get_frame_entity(node) == NULL) {
223 be_fec_env_t *env = (be_fec_env_t*)data;
224 const ir_mode *mode = get_irn_mode(node);
225 int align = get_mode_size_bytes(mode);
226 be_node_needs_frame_entity(env, node, mode, align);
231 * Called immediatly before emit phase.
233 static void amd64_finish_irg(ir_graph *irg)
235 be_stack_layout_t *stack_layout = be_get_irg_stack_layout(irg);
236 bool at_begin = stack_layout->sp_relative ? true : false;
237 be_fec_env_t *fec_env = be_new_frame_entity_coalescer(irg);
239 /* create and coalesce frame entities */
240 irg_walk_graph(irg, NULL, amd64_collect_frame_entity_nodes, fec_env);
241 be_assign_entities(fec_env, amd64_set_frame_entity, at_begin);
242 be_free_frame_entity_coalescer(fec_env);
244 irg_block_walk_graph(irg, NULL, amd64_after_ra_walker, NULL);
246 /* fix stack entity offsets */
247 be_abi_fix_stack_nodes(irg);
248 be_abi_fix_stack_bias(irg);
252 * Initializes the code generator.
254 static void amd64_init_graph(ir_graph *irg)
256 struct obstack *obst = be_get_be_obst(irg);
257 amd64_irg_data_t *irg_data = OALLOCZ(obst, amd64_irg_data_t);
258 irg_data->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
260 be_birg_from_irg(irg)->isa_link = irg_data;
264 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
267 * Used to create per-graph unique pseudo nodes.
269 static inline ir_node *create_const(ir_graph *irg, ir_node **place,
270 create_const_node_func func,
271 const arch_register_t* reg)
273 ir_node *block, *res;
278 block = get_irg_start_block(irg);
279 res = func(NULL, block);
280 arch_set_irn_register(res, reg);
286 extern const arch_isa_if_t amd64_isa_if;
287 static amd64_isa_t amd64_isa_template = {
289 &amd64_isa_if, /* isa interface implementation */
294 &amd64_registers[REG_RSP], /* stack pointer register */
295 &amd64_registers[REG_RBP], /* base pointer register */
296 &amd64_reg_classes[CLASS_amd64_gp], /* link pointer register class */
297 3, /* power of two stack alignment for calls, 2^2 == 4 */
298 NULL, /* main environment */
299 7, /* costs for a spill instruction */
300 5, /* costs for a reload instruction */
301 false, /* no custom abi handling */
306 * Initializes the backend ISA
308 static arch_env_t *amd64_init(FILE *outfile)
310 amd64_isa_t *isa = XMALLOC(amd64_isa_t);
311 *isa = amd64_isa_template;
313 be_emit_init(outfile);
315 amd64_register_init();
316 amd64_create_opcodes(&amd64_irn_ops);
324 * Closes the output file and frees the ISA structure.
326 static void amd64_done(void *self)
328 amd64_isa_t *isa = (amd64_isa_t*)self;
330 /* emit now all global declarations */
331 be_gas_emit_decls(isa->base.main_env);
339 * Get the register class which shall be used to store a value of a given mode.
340 * @param self The this pointer.
341 * @param mode The mode in question.
342 * @return A register class which can hold values of the given mode.
344 static const arch_register_class_t *amd64_get_reg_class_for_mode(const ir_mode *mode)
346 assert(!mode_is_float(mode));
347 return &amd64_reg_classes[CLASS_amd64_gp];
353 be_abi_call_flags_bits_t flags;
358 * Get the between type for that call.
359 * @param self The callback object.
360 * @return The between type of for that call.
362 static ir_type *amd64_get_between_type(ir_graph *irg)
364 static ir_type *between_type = NULL;
365 static ir_entity *old_bp_ent = NULL;
369 ir_entity *ret_addr_ent;
370 ir_type *ret_addr_type = new_type_primitive(mode_P);
371 ir_type *old_bp_type = new_type_primitive(mode_P);
373 between_type = new_type_class(new_id_from_str("amd64_between_type"));
374 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
375 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
377 set_entity_offset(old_bp_ent, 0);
378 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
379 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
385 static const be_abi_callbacks_t amd64_abi_callbacks = {
386 amd64_get_between_type,
389 static const arch_register_t *gpreg_param_reg_std[] = {
390 &amd64_registers[REG_RDI],
391 &amd64_registers[REG_RSI],
392 &amd64_registers[REG_RDX],
393 &amd64_registers[REG_RCX],
394 &amd64_registers[REG_R8],
395 &amd64_registers[REG_R9],
398 static const arch_register_t *amd64_get_RegParam_reg(int n)
400 assert(n < 6 && n >=0 && "register param > 6 requested");
401 return gpreg_param_reg_std[n];
405 * Get the ABI restrictions for procedure calls.
406 * @param self The this pointer.
407 * @param method_type The type of the method (procedure) in question.
408 * @param abi The abi object to be modified
410 static void amd64_get_call_abi(const void *self, ir_type *method_type,
415 int i, n = get_method_n_params(method_type);
416 be_abi_call_flags_t call_flags;
421 /* set abi flags for calls */
422 call_flags.bits.store_args_sequential = 0;
423 call_flags.bits.try_omit_fp = 1;
424 call_flags.bits.fp_free = 0;
425 call_flags.bits.call_has_imm = 1;
427 /* set stack parameter passing style */
428 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
430 for (i = 0; i < n; i++) {
431 tp = get_method_param_type(method_type, i);
432 mode = get_type_mode(tp);
433 //d// printf ("MODE %p %p XX %d\n", mode, mode_Iu, i);
435 if (!no_reg && i < 6 && mode_is_data (mode)) {
436 //d// printf("TEST%d\n", i);
437 be_abi_call_param_reg(abi, i, amd64_get_RegParam_reg (i),
439 /* default: all parameters on stack */
442 be_abi_call_param_stack(abi, i, mode, 8, 0, 0, ABI_CONTEXT_BOTH);
446 /* TODO: set correct return register */
447 /* default: return value is in R0 resp. F0 */
448 if (get_method_n_ress(method_type) > 0) {
449 tp = get_method_res_type(method_type, 0);
450 mode = get_type_mode(tp);
452 /* FIXME: No floating point yet */
453 /* be_abi_call_res_reg(abi, 0,
454 mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_registers[REG_R0], ABI_CONTEXT_BOTH); */
456 be_abi_call_res_reg(abi, 0,
457 &amd64_registers[REG_RAX], ABI_CONTEXT_BOTH);
462 * Returns the necessary byte alignment for storing a register of given class.
464 static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
466 ir_mode *mode = arch_register_class_mode(cls);
467 return get_mode_size_bytes(mode);
470 static void amd64_lower_for_target(void)
472 /* lower compound param handling */
473 lower_calls_with_compounds(LF_RETURN_HIDDEN);
476 static int amd64_is_mux_allowed(ir_node *sel, ir_node *mux_false,
486 * Returns the libFirm configuration parameter for this backend.
488 static const backend_params *amd64_get_backend_params(void) {
489 static backend_params p = {
490 0, /* no inline assembly */
491 1, /* support Rotl nodes */
492 0, /* little endian */
493 1, /* modulo shift is efficient */
494 0, /* non-modulo shift is not efficient */
495 NULL, /* will be set later */
496 amd64_is_mux_allowed, /* parameter for if conversion */
497 64, /* machine size */
498 NULL, /* float arithmetic mode */
499 NULL, /* long long type */
500 NULL, /* unsigned long long type */
501 NULL, /* long double type (not supported yet) */
502 0, /* no trampoline support: size 0 */
503 0, /* no trampoline support: align 0 */
504 NULL, /* no trampoline support: no trampoline builder */
505 8 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
510 static ir_graph **amd64_get_backend_irg_list(const void *self,
518 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
521 return ASM_CONSTRAINT_FLAG_INVALID;
524 static int amd64_is_valid_clobber(const char *clobber)
530 static int amd64_register_saved_by(const arch_register_t *reg, int callee)
533 /* check for callee saved */
534 if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_gp]) {
535 switch (reg->index) {
548 /* check for caller saved */
549 if (reg->reg_class == &amd64_reg_classes[CLASS_amd64_gp]) {
550 switch (reg->index) {
569 const arch_isa_if_t amd64_isa_if = {
571 amd64_lower_for_target,
573 NULL, /* handle intrinsics */
574 amd64_get_reg_class_for_mode,
576 amd64_get_reg_class_alignment,
577 amd64_get_backend_params,
578 amd64_get_backend_irg_list,
579 NULL, /* mark remat */
580 amd64_parse_asm_constraint,
581 amd64_is_valid_clobber,
584 NULL, /* get_pic_base */
585 NULL, /* before_abi */
590 amd64_register_saved_by,
593 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64)
594 void be_init_arch_amd64(void)
596 be_register_isa_if("amd64", &amd64_isa_if);
597 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
598 amd64_init_transform();