2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
23 * @version $Id: bearch_amd64.c 26909 2010-01-05 15:56:54Z matze $
38 #include "../bearch.h"
39 #include "../benode.h"
40 #include "../belower.h"
41 #include "../besched.h"
43 #include "../bemodule.h"
44 #include "../begnuas.h"
45 #include "../belistsched.h"
46 #include "../beflags.h"
47 #include "../bespillslots.h"
49 #include "bearch_amd64_t.h"
51 #include "amd64_new_nodes.h"
52 #include "gen_amd64_regalloc_if.h"
53 #include "amd64_transform.h"
54 #include "amd64_emitter.h"
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 static arch_irn_class_t amd64_classify(const ir_node *irn)
64 static ir_entity *amd64_get_frame_entity(const ir_node *node)
66 if (is_amd64_FrameAddr(node)) {
67 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
70 } else if (is_amd64_Store(node)) {
71 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
74 } else if (is_amd64_Load(node)) {
75 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(node);
80 /* TODO: return the ir_entity assigned to the frame */
85 * This function is called by the generic backend to correct offsets for
86 * nodes accessing the stack.
88 static void amd64_set_frame_offset(ir_node *irn, int offset)
90 if (is_amd64_FrameAddr(irn)) {
91 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
92 attr->fp_offset += offset;
94 } else if (is_amd64_Store(irn)) {
95 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
96 attr->fp_offset += offset;
98 } else if (is_amd64_Load(irn)) {
99 amd64_SymConst_attr_t *attr = get_irn_generic_attr(irn);
100 attr->fp_offset += offset;
105 static int amd64_get_sp_bias(const ir_node *irn)
111 /* fill register allocator interface */
113 static const arch_irn_ops_t amd64_irn_ops = {
116 amd64_get_frame_entity,
117 amd64_set_frame_offset,
119 NULL, /* get_inverse */
120 NULL, /* get_op_estimated_cost */
121 NULL, /* possible_memory_operand */
122 NULL, /* perform_memory_operand */
128 * Transforms the standard firm graph into
131 static void amd64_prepare_graph(void *self)
133 amd64_code_gen_t *cg = self;
135 amd64_transform_graph (cg);
138 dump_ir_graph(cg->irg, "transformed");
143 * Called immediatly before emit phase.
145 static void amd64_finish_irg(void *self)
147 amd64_code_gen_t *cg = self;
148 ir_graph *irg = cg->irg;
150 dump_ir_graph(irg, "amd64-finished");
153 static void amd64_before_ra(void *self)
155 amd64_code_gen_t *cg = self;
157 be_sched_fix_flags(cg->irg, &amd64_reg_classes[CLASS_amd64_flags], 0);
161 static void transform_Reload(ir_node *node)
163 ir_graph *irg = get_irn_irg(node);
164 ir_node *block = get_nodes_block(node);
165 dbg_info *dbgi = get_irn_dbg_info(node);
166 ir_node *ptr = get_irg_frame(irg);
167 ir_node *mem = get_irn_n(node, be_pos_Reload_mem);
168 ir_mode *mode = get_irn_mode(node);
169 ir_entity *entity = be_get_frame_entity(node);
170 const arch_register_t *reg;
174 ir_node *sched_point = sched_prev(node);
176 load = new_bd_amd64_Load(dbgi, block, ptr, mem, entity);
177 sched_add_after(sched_point, load);
180 proj = new_rd_Proj(dbgi, load, mode, pn_amd64_Load_res);
182 reg = arch_get_irn_register(node);
183 arch_set_irn_register(proj, reg);
185 exchange(node, proj);
188 static void transform_Spill(ir_node *node)
190 ir_graph *irg = get_irn_irg(node);
191 ir_node *block = get_nodes_block(node);
192 dbg_info *dbgi = get_irn_dbg_info(node);
193 ir_node *ptr = get_irg_frame(irg);
194 ir_node *mem = new_NoMem();
195 ir_node *val = get_irn_n(node, be_pos_Spill_val);
196 //ir_mode *mode = get_irn_mode(val);
197 ir_entity *entity = be_get_frame_entity(node);
198 ir_node *sched_point;
201 sched_point = sched_prev(node);
202 store = new_bd_amd64_Store(dbgi, block, ptr, val, mem, entity);
205 sched_add_after(sched_point, store);
207 exchange(node, store);
210 static void amd64_after_ra_walker(ir_node *block, void *data)
212 ir_node *node, *prev;
215 for (node = sched_last(block); !sched_is_begin(node); node = prev) {
216 prev = sched_prev(node);
218 if (be_is_Reload(node)) {
219 transform_Reload(node);
220 } else if (be_is_Spill(node)) {
221 transform_Spill(node);
226 static void amd64_after_ra(void *self)
228 amd64_code_gen_t *cg = self;
229 be_coalesce_spillslots(cg->irg);
231 irg_block_walk_graph(cg->irg, NULL, amd64_after_ra_walker, NULL);
236 * Emits the code, closes the output file and frees
237 * the code generator interface.
239 static void amd64_emit_and_done(void *self)
241 amd64_code_gen_t *cg = self;
242 ir_graph *irg = cg->irg;
244 amd64_gen_routine(cg, irg);
246 /* de-allocate code generator */
250 static void *amd64_cg_init(ir_graph *irg);
252 static const arch_code_generator_if_t amd64_code_gen_if = {
254 NULL, /* get_pic_base hook */
255 NULL, /* before abi introduce hook */
257 NULL, /* spill hook */
258 amd64_before_ra, /* before register allocation hook */
259 amd64_after_ra, /* after register allocation hook */
265 * Initializes the code generator.
267 static void *amd64_cg_init(ir_graph *irg)
269 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
270 amd64_isa_t *isa = (amd64_isa_t *) arch_env;
271 amd64_code_gen_t *cg = XMALLOC(amd64_code_gen_t);
273 cg->impl = &amd64_code_gen_if;
276 cg->dump = (be_get_irg_options(irg)->dump_flags & DUMP_BE) ? 1 : 0;
278 return (arch_code_generator_t *)cg;
282 typedef ir_node *(*create_const_node_func) (dbg_info *dbg, ir_node *block);
285 * Used to create per-graph unique pseudo nodes.
287 static inline ir_node *create_const(amd64_code_gen_t *cg, ir_node **place,
288 create_const_node_func func,
289 const arch_register_t* reg)
291 ir_node *block, *res;
296 block = get_irg_start_block(cg->irg);
297 res = func(NULL, block);
298 arch_set_irn_register(res, reg);
304 const arch_isa_if_t amd64_isa_if;
305 static amd64_isa_t amd64_isa_template = {
307 &amd64_isa_if, /* isa interface implementation */
308 &amd64_gp_regs[REG_RSP], /* stack pointer register */
309 &amd64_gp_regs[REG_RBP], /* base pointer register */
310 &amd64_reg_classes[CLASS_amd64_gp], /* link pointer register class */
311 -1, /* stack direction */
312 3, /* power of two stack alignment for calls, 2^2 == 4 */
313 NULL, /* main environment */
314 7, /* costs for a spill instruction */
315 5, /* costs for a reload instruction */
316 false, /* no custom abi handling */
321 * Initializes the backend ISA
323 static arch_env_t *amd64_init(FILE *outfile)
325 static int run_once = 0;
332 isa = XMALLOC(amd64_isa_t);
333 memcpy(isa, &amd64_isa_template, sizeof(*isa));
335 be_emit_init(outfile);
337 amd64_register_init();
338 amd64_create_opcodes(&amd64_irn_ops);
346 * Closes the output file and frees the ISA structure.
348 static void amd64_done(void *self)
350 amd64_isa_t *isa = self;
352 /* emit now all global declarations */
353 be_gas_emit_decls(isa->base.main_env);
360 static unsigned amd64_get_n_reg_class(void)
365 static const arch_register_class_t *amd64_get_reg_class(unsigned i)
367 assert(i < N_CLASSES);
368 return &amd64_reg_classes[i];
374 * Get the register class which shall be used to store a value of a given mode.
375 * @param self The this pointer.
376 * @param mode The mode in question.
377 * @return A register class which can hold values of the given mode.
379 static const arch_register_class_t *amd64_get_reg_class_for_mode(const ir_mode *mode)
381 assert(!mode_is_float(mode));
382 return &amd64_reg_classes[CLASS_amd64_gp];
388 be_abi_call_flags_bits_t flags;
392 static void *amd64_abi_init(const be_abi_call_t *call, ir_graph *irg)
394 amd64_abi_env_t *env = XMALLOC(amd64_abi_env_t);
395 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
396 env->flags = fl.bits;
402 * Get the between type for that call.
403 * @param self The callback object.
404 * @return The between type of for that call.
406 static ir_type *amd64_get_between_type(void *self)
408 static ir_type *between_type = NULL;
409 static ir_entity *old_bp_ent = NULL;
413 ir_entity *ret_addr_ent;
414 ir_type *ret_addr_type = new_type_primitive(mode_P);
415 ir_type *old_bp_type = new_type_primitive(mode_P);
417 between_type = new_type_class(new_id_from_str("amd64_between_type"));
418 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
419 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
421 set_entity_offset(old_bp_ent, 0);
422 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
423 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
430 * Build the prolog, return the BASE POINTER register
432 static const arch_register_t *amd64_abi_prologue(void *self, ir_node **mem,
433 pmap *reg_map, int *stack_bias)
435 amd64_abi_env_t *env = self;
436 const arch_env_t *aenv = be_get_irg_arch_env(env->irg);
442 if (!env->flags.try_omit_fp) {
443 /* FIXME: maybe later here should be some code to generate
444 * the usual abi prologue */
451 /* Build the epilog */
452 static void amd64_abi_epilogue(void *self, ir_node *bl, ir_node **mem,
455 amd64_abi_env_t *env = self;
456 const arch_env_t *aenv = be_get_irg_arch_env(env->irg);
457 ir_node *curr_sp = be_abi_reg_map_get(reg_map, aenv->sp);
458 ir_node *curr_bp = be_abi_reg_map_get(reg_map, aenv->bp);
462 if (env->flags.try_omit_fp) {
463 curr_sp = be_new_IncSP(aenv->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
466 be_abi_reg_map_set(reg_map, aenv->sp, curr_sp);
467 be_abi_reg_map_set(reg_map, aenv->bp, curr_bp);
470 static const be_abi_callbacks_t amd64_abi_callbacks = {
473 amd64_get_between_type,
478 static const arch_register_t *gpreg_param_reg_std[] = {
479 &amd64_gp_regs[REG_RDI],
480 &amd64_gp_regs[REG_RSI],
481 &amd64_gp_regs[REG_RDX],
482 &amd64_gp_regs[REG_RCX],
483 &amd64_gp_regs[REG_R8],
484 &amd64_gp_regs[REG_R9],
487 static const arch_register_t *amd64_get_RegParam_reg(int n)
489 assert(n < 6 && n >=0 && "register param > 6 requested");
490 return gpreg_param_reg_std[n];
494 * Get the ABI restrictions for procedure calls.
495 * @param self The this pointer.
496 * @param method_type The type of the method (procedure) in question.
497 * @param abi The abi object to be modified
499 static void amd64_get_call_abi(const void *self, ir_type *method_type,
504 int i, n = get_method_n_params(method_type);
505 be_abi_call_flags_t call_flags;
510 /* set abi flags for calls */
511 call_flags.bits.left_to_right = 0;
512 call_flags.bits.store_args_sequential = 0;
513 call_flags.bits.try_omit_fp = 1;
514 call_flags.bits.fp_free = 0;
515 call_flags.bits.call_has_imm = 1;
517 /* set stack parameter passing style */
518 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
520 for (i = 0; i < n; i++) {
521 tp = get_method_param_type(method_type, i);
522 mode = get_type_mode(tp);
523 //d// printf ("MODE %p %p XX %d\n", mode, mode_Iu, i);
525 if (!no_reg && i < 6 && mode_is_data (mode)) {
526 //d// printf("TEST%d\n", i);
527 be_abi_call_param_reg(abi, i, amd64_get_RegParam_reg (i),
529 /* default: all parameters on stack */
532 be_abi_call_param_stack(abi, i, mode, 8, 0, 0, ABI_CONTEXT_BOTH);
536 /* TODO: set correct return register */
537 /* default: return value is in R0 resp. F0 */
538 if (get_method_n_ress(method_type) > 0) {
539 tp = get_method_res_type(method_type, 0);
540 mode = get_type_mode(tp);
542 /* FIXME: No floating point yet */
543 /* be_abi_call_res_reg(abi, 0,
544 mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_gp_regs[REG_R0], ABI_CONTEXT_BOTH) */;
546 be_abi_call_res_reg(abi, 0,
547 &amd64_gp_regs[REG_RAX], ABI_CONTEXT_BOTH);
551 static int amd64_to_appear_in_schedule(void *block_env, const ir_node *irn)
555 if(!is_amd64_irn(irn))
562 * Initializes the code generator interface.
564 static const arch_code_generator_if_t *amd64_get_code_generator_if(
568 return &amd64_code_gen_if;
571 list_sched_selector_t amd64_sched_selector;
574 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
576 static const list_sched_selector_t *amd64_get_list_sched_selector(
577 const void *self, list_sched_selector_t *selector)
582 amd64_sched_selector = trivial_selector;
583 amd64_sched_selector.to_appear_in_schedule = amd64_to_appear_in_schedule;
584 return &amd64_sched_selector;
587 static const ilp_sched_selector_t *amd64_get_ilp_sched_selector(
595 * Returns the necessary byte alignment for storing a register of given class.
597 static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
599 ir_mode *mode = arch_register_class_mode(cls);
600 return get_mode_size_bytes(mode);
604 * Returns the libFirm configuration parameter for this backend.
606 static const backend_params *amd64_get_backend_params(void) {
607 static backend_params p = {
608 0, /* no dword lowering */
609 0, /* no inline assembly */
610 NULL, /* will be set later */
611 NULL, /* no creator function */
612 NULL, /* context for create_intrinsic_fkt */
613 NULL, /* parameter for if conversion */
614 NULL, /* float arithmetic mode */
615 0, /* no trampoline support: size 0 */
616 0, /* no trampoline support: align 0 */
617 NULL, /* no trampoline support: no trampoline builder */
618 8 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
623 static const be_execution_unit_t ***amd64_get_allowed_execution_units(
632 static const be_machine_t *amd64_get_machine(const void *self)
640 static ir_graph **amd64_get_backend_irg_list(const void *self,
648 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
651 return ASM_CONSTRAINT_FLAG_INVALID;
654 static int amd64_is_valid_clobber(const char *clobber)
660 const arch_isa_if_t amd64_isa_if = {
663 NULL, /* handle intrinsics */
664 amd64_get_n_reg_class,
666 amd64_get_reg_class_for_mode,
668 amd64_get_code_generator_if,
669 amd64_get_list_sched_selector,
670 amd64_get_ilp_sched_selector,
671 amd64_get_reg_class_alignment,
672 amd64_get_backend_params,
673 amd64_get_allowed_execution_units,
675 amd64_get_backend_irg_list,
676 NULL, /* mark remat */
677 amd64_parse_asm_constraint,
678 amd64_is_valid_clobber
681 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64);
682 void be_init_arch_amd64(void)
684 be_register_isa_if("amd64", &amd64_isa_if);
685 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
686 amd64_init_transform();