2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief The main amd64 backend driver file.
23 * @version $Id: bearch_amd64.c 26909 2010-01-05 15:56:54Z matze $
27 #include "pseudo_irg.h"
39 #include "../bearch.h"
40 #include "../benode.h"
41 #include "../belower.h"
42 #include "../besched.h"
44 #include "../bemodule.h"
45 #include "../begnuas.h"
46 #include "../belistsched.h"
48 #include "bearch_amd64_t.h"
50 #include "amd64_new_nodes.h"
51 #include "gen_amd64_regalloc_if.h"
52 #include "amd64_transform.h"
53 #include "amd64_emitter.h"
55 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
57 static arch_irn_class_t amd64_classify(const ir_node *irn)
63 static ir_entity *amd64_get_frame_entity(const ir_node *node)
66 /* TODO: return the ir_entity assigned to the frame */
70 static void amd64_set_frame_entity(ir_node *node, ir_entity *ent)
74 /* TODO: set the ir_entity assigned to the frame */
78 * This function is called by the generic backend to correct offsets for
79 * nodes accessing the stack.
81 static void amd64_set_frame_offset(ir_node *irn, int offset)
85 /* TODO: correct offset if irn accesses the stack */
88 static int amd64_get_sp_bias(const ir_node *irn)
94 /* fill register allocator interface */
96 static const arch_irn_ops_t amd64_irn_ops = {
99 amd64_get_frame_entity,
100 amd64_set_frame_entity,
101 amd64_set_frame_offset,
103 NULL, /* get_inverse */
104 NULL, /* get_op_estimated_cost */
105 NULL, /* possible_memory_operand */
106 NULL, /* perform_memory_operand */
112 * Transforms the standard firm graph into
115 static void amd64_prepare_graph(void *self)
117 amd64_code_gen_t *cg = self;
119 amd64_transform_graph (cg);
122 dump_ir_graph(cg->irg, "transformed");
128 * Called immediatly before emit phase.
130 static void amd64_finish_irg(void *self)
132 amd64_code_gen_t *cg = self;
133 ir_graph *irg = cg->irg;
135 dump_ir_graph(irg, "amd64-finished");
139 static void amd64_before_ra(void *self)
142 /* Some stuff you need to do after scheduling but before register allocation */
145 static void amd64_after_ra(void *self)
148 /* Some stuff you need to do immediatly after register allocation */
154 * Emits the code, closes the output file and frees
155 * the code generator interface.
157 static void amd64_emit_and_done(void *self)
159 amd64_code_gen_t *cg = self;
160 ir_graph *irg = cg->irg;
162 amd64_gen_routine(cg, irg);
164 /* de-allocate code generator */
168 static void *amd64_cg_init(be_irg_t *birg);
170 static const arch_code_generator_if_t amd64_code_gen_if = {
172 NULL, /* get_pic_base hook */
173 NULL, /* before abi introduce hook */
175 NULL, /* spill hook */
176 amd64_before_ra, /* before register allocation hook */
177 amd64_after_ra, /* after register allocation hook */
183 * Initializes the code generator.
185 static void *amd64_cg_init(be_irg_t *birg)
187 const arch_env_t *arch_env = be_get_birg_arch_env(birg);
188 amd64_isa_t *isa = (amd64_isa_t *) arch_env;
189 amd64_code_gen_t *cg = XMALLOC(amd64_code_gen_t);
191 cg->impl = &amd64_code_gen_if;
192 cg->irg = be_get_birg_irg(birg);
195 cg->dump = (birg->main_env->options->dump_flags & DUMP_BE) ? 1 : 0;
197 return (arch_code_generator_t *)cg;
202 const arch_isa_if_t amd64_isa_if;
203 static amd64_isa_t amd64_isa_template = {
205 &amd64_isa_if, /* isa interface implementation */
206 &amd64_gp_regs[REG_RSP], /* stack pointer register */
207 &amd64_gp_regs[REG_RBP], /* base pointer register */
208 &amd64_reg_classes[CLASS_amd64_gp], /* link pointer register class */
209 -1, /* stack direction */
210 2, /* power of two stack alignment for calls, 2^2 == 4 */
211 NULL, /* main environment */
212 7, /* costs for a spill instruction */
213 5, /* costs for a reload instruction */
218 * Initializes the backend ISA
220 static arch_env_t *amd64_init(FILE *outfile)
222 static int run_once = 0;
229 isa = XMALLOC(amd64_isa_t);
230 memcpy(isa, &amd64_isa_template, sizeof(*isa));
232 be_emit_init(outfile);
234 amd64_register_init();
235 amd64_create_opcodes(&amd64_irn_ops);
237 return &isa->arch_env;
243 * Closes the output file and frees the ISA structure.
245 static void amd64_done(void *self)
247 amd64_isa_t *isa = self;
249 /* emit now all global declarations */
250 be_gas_emit_decls(isa->arch_env.main_env);
257 static unsigned amd64_get_n_reg_class(void)
262 static const arch_register_class_t *amd64_get_reg_class(unsigned i)
264 assert(i < N_CLASSES);
265 return &amd64_reg_classes[i];
271 * Get the register class which shall be used to store a value of a given mode.
272 * @param self The this pointer.
273 * @param mode The mode in question.
274 * @return A register class which can hold values of the given mode.
276 static const arch_register_class_t *amd64_get_reg_class_for_mode(const ir_mode *mode)
278 if (mode_is_float(mode))
279 return &amd64_reg_classes[CLASS_amd64_fp];
281 return &amd64_reg_classes[CLASS_amd64_gp];
287 be_abi_call_flags_bits_t flags;
288 const arch_env_t *arch_env;
292 static void *amd64_abi_init(const be_abi_call_t *call, const arch_env_t *arch_env, ir_graph *irg)
294 amd64_abi_env_t *env = XMALLOC(amd64_abi_env_t);
295 be_abi_call_flags_t fl = be_abi_call_get_flags(call);
296 env->flags = fl.bits;
298 env->arch_env = arch_env;
303 * Get the between type for that call.
304 * @param self The callback object.
305 * @return The between type of for that call.
307 static ir_type *amd64_get_between_type(void *self)
309 static ir_type *between_type = NULL;
310 static ir_entity *old_bp_ent = NULL;
314 ir_entity *ret_addr_ent;
315 ir_type *ret_addr_type = new_type_primitive(mode_P);
316 ir_type *old_bp_type = new_type_primitive(mode_P);
318 between_type = new_type_class(new_id_from_str("amd64_between_type"));
319 old_bp_ent = new_entity(between_type, new_id_from_str("old_bp"), old_bp_type);
320 ret_addr_ent = new_entity(between_type, new_id_from_str("old_bp"), ret_addr_type);
322 set_entity_offset(old_bp_ent, 0);
323 set_entity_offset(ret_addr_ent, get_type_size_bytes(old_bp_type));
324 set_type_size_bytes(between_type, get_type_size_bytes(old_bp_type) + get_type_size_bytes(ret_addr_type));
331 * Build the prolog, return the BASE POINTER register
333 static const arch_register_t *amd64_abi_prologue(void *self, ir_node **mem,
334 pmap *reg_map, int *stack_bias)
336 amd64_abi_env_t *env = self;
337 const arch_env_t *aenv = env->arch_env;
343 if (!env->flags.try_omit_fp) {
344 /* FIXME: maybe later here should be some code to generate
345 * the usual abi prologue */
346 return env->arch_env->bp;
349 return env->arch_env->sp;
352 /* Build the epilog */
353 static void amd64_abi_epilogue(void *self, ir_node *bl, ir_node **mem,
356 amd64_abi_env_t *env = self;
357 const arch_env_t *aenv = env->arch_env;
358 ir_node *curr_sp = be_abi_reg_map_get(reg_map, aenv->sp);
359 ir_node *curr_bp = be_abi_reg_map_get(reg_map, aenv->bp);
363 if (env->flags.try_omit_fp) {
364 curr_sp = be_new_IncSP(aenv->sp, bl, curr_sp, BE_STACK_FRAME_SIZE_SHRINK, 0);
367 be_abi_reg_map_set(reg_map, aenv->sp, curr_sp);
368 be_abi_reg_map_set(reg_map, aenv->bp, curr_bp);
371 static const be_abi_callbacks_t amd64_abi_callbacks = {
374 amd64_get_between_type,
380 * Get the ABI restrictions for procedure calls.
381 * @param self The this pointer.
382 * @param method_type The type of the method (procedure) in question.
383 * @param abi The abi object to be modified
385 static void amd64_get_call_abi(const void *self, ir_type *method_type,
390 int i, n = get_method_n_params(method_type);
391 be_abi_call_flags_t call_flags;
396 /* set abi flags for calls */
397 call_flags.bits.left_to_right = 0;
398 call_flags.bits.store_args_sequential = 1;
399 call_flags.bits.try_omit_fp = 1;
400 call_flags.bits.fp_free = 0;
401 call_flags.bits.call_has_imm = 1;
403 /* set stack parameter passing style */
404 be_abi_call_set_flags(abi, call_flags, &amd64_abi_callbacks);
406 for (i = 0; i < n; i++) {
407 tp = get_method_param_type(method_type, i);
408 mode = get_type_mode(tp);
409 printf ("MODE %p %p XX %d\n", mode, mode_Iu, i);
411 if (!no_reg && (i == 0 || i == 1) && mode == mode_Iu) {
412 printf("TEST%d\n", i);
413 be_abi_call_param_reg(abi, i,
414 i == 0 ? &amd64_gp_regs[REG_RDI]
415 : &amd64_gp_regs[REG_RSI],
417 /* default: all parameters on stack */
420 be_abi_call_param_stack(abi, i, mode, 4, 0, 0, ABI_CONTEXT_BOTH);
424 /* TODO: set correct return register */
425 /* default: return value is in R0 resp. F0 */
426 if (get_method_n_ress(method_type) > 0) {
427 tp = get_method_res_type(method_type, 0);
428 mode = get_type_mode(tp);
430 /* FIXME: No floating point yet */
431 /* be_abi_call_res_reg(abi, 0,
432 mode_is_float(mode) ? &amd64_fp_regs[REG_F0] : &amd64_gp_regs[REG_R0], ABI_CONTEXT_BOTH) */;
434 be_abi_call_res_reg(abi, 0,
435 &amd64_gp_regs[REG_RAX], ABI_CONTEXT_BOTH);
439 static int amd64_to_appear_in_schedule(void *block_env, const ir_node *irn)
443 if(!is_amd64_irn(irn))
450 * Initializes the code generator interface.
452 static const arch_code_generator_if_t *amd64_get_code_generator_if(
456 return &amd64_code_gen_if;
459 list_sched_selector_t amd64_sched_selector;
462 * Returns the reg_pressure scheduler with to_appear_in_schedule() overloaded
464 static const list_sched_selector_t *amd64_get_list_sched_selector(
465 const void *self, list_sched_selector_t *selector)
470 amd64_sched_selector = trivial_selector;
471 amd64_sched_selector.to_appear_in_schedule = amd64_to_appear_in_schedule;
472 return &amd64_sched_selector;
475 static const ilp_sched_selector_t *amd64_get_ilp_sched_selector(
483 * Returns the necessary byte alignment for storing a register of given class.
485 static int amd64_get_reg_class_alignment(const arch_register_class_t *cls)
487 ir_mode *mode = arch_register_class_mode(cls);
488 return get_mode_size_bytes(mode);
492 * Returns the libFirm configuration parameter for this backend.
494 static const backend_params *amd64_get_backend_params(void) {
495 static backend_params p = {
496 0, /* no dword lowering */
497 0, /* no inline assembly */
498 NULL, /* will be set later */
499 NULL, /* no creator function */
500 NULL, /* context for create_intrinsic_fkt */
501 NULL, /* parameter for if conversion */
502 NULL, /* float arithmetic mode */
503 0, /* no trampoline support: size 0 */
504 0, /* no trampoline support: align 0 */
505 NULL, /* no trampoline support: no trampoline builder */
506 4 /* alignment of stack parameter: typically 4 (32bit) or 8 (64bit) */
511 static const be_execution_unit_t ***amd64_get_allowed_execution_units(
520 static const be_machine_t *amd64_get_machine(const void *self)
528 static ir_graph **amd64_get_backend_irg_list(const void *self,
536 static asm_constraint_flags_t amd64_parse_asm_constraint(const char **c)
539 return ASM_CONSTRAINT_FLAG_INVALID;
542 static int amd64_is_valid_clobber(const char *clobber)
548 const arch_isa_if_t amd64_isa_if = {
551 NULL, /* handle intrinsics */
552 amd64_get_n_reg_class,
554 amd64_get_reg_class_for_mode,
556 amd64_get_code_generator_if,
557 amd64_get_list_sched_selector,
558 amd64_get_ilp_sched_selector,
559 amd64_get_reg_class_alignment,
560 amd64_get_backend_params,
561 amd64_get_allowed_execution_units,
563 amd64_get_backend_irg_list,
564 NULL, /* mark remat */
565 amd64_parse_asm_constraint,
566 amd64_is_valid_clobber
569 BE_REGISTER_MODULE_CONSTRUCTOR(be_init_arch_amd64);
570 void be_init_arch_amd64(void)
572 be_register_isa_if("amd64", &amd64_isa_if);
573 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.cg");
574 amd64_init_transform();