2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
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8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into amd64 FIRM)
23 * @version $Id: amd64_transform.c 26673 2009-10-01 16:43:13Z matze $
28 #include "irgraph_t.h"
38 #include "../benode.h"
39 #include "../betranshlp.h"
40 #include "../beutil.h"
41 #include "bearch_amd64_t.h"
43 #include "amd64_nodes_attr.h"
44 #include "amd64_transform.h"
45 #include "amd64_new_nodes.h"
47 #include "gen_amd64_regalloc_if.h"
49 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
51 /** holds the current code generator during transformation */
52 static amd64_code_gen_t *env_cg;
54 ///* its enough to have those once */
55 //static ir_node *nomem, *noreg_GP;
57 /* Some support functions: */
59 static inline int mode_needs_gp_reg(ir_mode *mode)
61 return mode_is_int(mode) || mode_is_reference(mode);
65 * Create a DAG constructing a given Const.
67 * @param irn a Firm const
69 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
71 tarval *tv = get_Const_tarval(irn);
72 ir_mode *mode = get_tarval_mode(tv);
73 dbg_info *dbgi = get_irn_dbg_info(irn);
76 if (mode_is_reference(mode)) {
77 /* AMD64 is 64bit, so we can safely convert a reference tarval into Iu */
78 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Lu));
79 tv = tarval_convert_to(tv, mode_Lu);
82 value = get_tarval_long(tv);
83 //d// printf ("TEST GENERATE %d\n", value);
85 return new_bd_amd64_Immediate(dbgi, block, value);
88 /* Op transformers: */
91 * Transforms a Const node.
93 * @return The transformed AMD64 node.
95 static ir_node *gen_Const(ir_node *node) {
96 ir_node *block = be_transform_node(get_nodes_block(node));
97 ir_mode *mode = get_irn_mode(node);
98 ir_node *res = create_const_graph(node, block);
101 be_dep_on_frame(res);
107 * Transforms a SymConst node.
109 * @return The transformed ARM node.
111 static ir_node *gen_SymConst(ir_node *node)
113 ir_node *block = be_transform_node(get_nodes_block(node));
114 ir_entity *entity = get_SymConst_entity(node);
115 dbg_info *dbgi = get_irn_dbg_info(node);
118 new_node = new_bd_amd64_SymConst(dbgi, block, entity);
119 be_dep_on_frame(new_node);
124 * Transforms an Add node.
126 * @return The transformed AMD64 node.
128 static ir_node *gen_Add(ir_node *node) {
129 ir_node *block = be_transform_node(get_nodes_block(node));
130 /* ir_mode *mode = get_irn_mode(node); */
131 ir_node *op1 = get_Add_left(node);
132 ir_node *op2 = get_Add_right(node);
133 dbg_info *dbgi = get_irn_dbg_info(node);
134 ir_node *new_op1 = be_transform_node(op1);
135 ir_node *new_op2 = be_transform_node(op2);
137 ir_node *res = new_bd_amd64_Add(dbgi, block, new_op1, new_op2);
138 be_dep_on_frame (res);
142 static ir_node *gen_Mul(ir_node *node) {
143 ir_node *block = be_transform_node(get_nodes_block(node));
144 /* ir_mode *mode = get_irn_mode(node); */
145 ir_node *op1 = get_Mul_left(node);
146 ir_node *op2 = get_Mul_right(node);
147 dbg_info *dbgi = get_irn_dbg_info(node);
148 ir_node *new_op1 = be_transform_node(op1);
149 ir_node *new_op2 = be_transform_node(op2);
151 ir_node *res = new_bd_amd64_Mul(dbgi, block, new_op1, new_op2);
152 be_dep_on_frame (res);
156 static ir_node *gen_Jmp(ir_node *node)
158 ir_node *block = get_nodes_block(node);
159 ir_node *new_block = be_transform_node(block);
160 dbg_info *dbgi = get_irn_dbg_info(node);
162 return new_bd_amd64_Jmp(dbgi, new_block);
165 static ir_node *gen_be_Call(ir_node *node)
167 ir_node *res = be_duplicate_node(node);
168 arch_irn_add_flags(res, arch_irn_flags_modify_flags);
173 static ir_node *gen_Cmp(ir_node *node)
175 ir_node *block = be_transform_node(get_nodes_block(node));
176 ir_node *op1 = get_Cmp_left(node);
177 ir_node *op2 = get_Cmp_right(node);
178 ir_mode *cmp_mode = get_irn_mode(op1);
179 dbg_info *dbgi = get_irn_dbg_info(node);
184 if (mode_is_float(cmp_mode)) {
185 panic("Floating point not implemented yet (in gen_Cmp)!");
188 assert(get_irn_mode(op2) == cmp_mode);
189 is_unsigned = !mode_is_signed(cmp_mode);
191 new_op1 = be_transform_node(op1);
192 // new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
193 new_op2 = be_transform_node(op2);
194 // new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
195 return new_bd_amd64_Cmp(dbgi, block, new_op1, new_op2, false,
202 * @return the created ARM Cond node
204 static ir_node *gen_Cond(ir_node *node)
206 ir_node *selector = get_Cond_selector(node);
207 ir_mode *mode = get_irn_mode(selector);
212 if (mode != mode_b) {
213 panic ("create_Switch not implemented yet!");
214 // return gen_SwitchJmp(node);
216 assert(is_Proj(selector));
218 block = be_transform_node(get_nodes_block(node));
219 dbgi = get_irn_dbg_info(node);
220 flag_node = be_transform_node(get_Proj_pred(selector));
222 return new_bd_amd64_Jcc(dbgi, block, flag_node, get_Proj_proj(selector));
226 // * Create an And that will zero out upper bits.
228 // * @param dbgi debug info
229 // * @param block the basic block
230 // * @param op the original node
231 // * param src_bits number of lower bits that will remain
233 //static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
236 // if (src_bits == 8) {
237 // return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
238 // } else if (src_bits == 16) {
239 // ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
240 // ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
243 // panic("zero extension only supported for 8 and 16 bits");
248 // * Generate code for a sign extension.
250 //static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
253 // int shift_width = 32 - src_bits;
254 // ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
255 // ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
256 // return rshift_node;
259 //static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
260 // ir_mode *orig_mode)
262 // int bits = get_mode_size_bits(orig_mode);
266 // if (mode_is_signed(orig_mode)) {
267 // return gen_sign_extension(dbgi, block, op, bits);
269 // return gen_zero_extension(dbgi, block, op, bits);
274 // * returns true if it is assured, that the upper bits of a node are "clean"
275 // * which means for a 16 or 8 bit value, that the upper bits in the register
276 // * are 0 for unsigned and a copy of the last significant bit for signed
279 //static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
281 // (void) transformed_node;
288 * Change some phi modes
290 static ir_node *gen_Phi(ir_node *node)
292 const arch_register_req_t *req;
293 ir_node *block = be_transform_node(get_nodes_block(node));
294 ir_graph *irg = current_ir_graph;
295 dbg_info *dbgi = get_irn_dbg_info(node);
296 ir_mode *mode = get_irn_mode(node);
299 if (mode_needs_gp_reg(mode)) {
300 /* all integer operations are on 64bit registers now */
302 req = amd64_reg_classes[CLASS_amd64_gp].class_req;
304 req = arch_no_register_req;
307 /* phi nodes allow loops, so we use the old arguments for now
308 * and fix this later */
309 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
310 get_irn_in(node) + 1);
311 copy_node_attr(irg, node, phi);
312 be_duplicate_deps(node, phi);
314 arch_set_out_register_req(phi, 0, req);
316 be_enqueue_preds(node);
324 * Transforms a Conv node.
326 * @return The created ia32 Conv node
328 static ir_node *gen_Conv(ir_node *node)
330 ir_node *block = be_transform_node(get_nodes_block(node));
331 ir_node *op = get_Conv_op(node);
332 ir_node *new_op = be_transform_node(op);
333 ir_mode *src_mode = get_irn_mode(op);
334 ir_mode *dst_mode = get_irn_mode(node);
335 dbg_info *dbgi = get_irn_dbg_info(node);
337 if (src_mode == dst_mode)
340 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
341 panic("float not supported yet");
342 } else { /* complete in gp registers */
343 int src_bits = get_mode_size_bits(src_mode);
344 int dst_bits = get_mode_size_bits(dst_mode);
348 if (src_bits == dst_bits) {
349 /* kill unneccessary conv */
353 if (src_bits < dst_bits) {
361 return new_bd_amd64_Conv(dbgi, block, new_op, min_mode);
363 //if (upper_bits_clean(new_op, min_mode)) {
367 //if (mode_is_signed(min_mode)) {
368 // return gen_sign_extension(dbg, block, new_op, min_bits);
370 // return gen_zero_extension(dbg, block, new_op, min_bits);
376 * Transforms a Store.
378 * @return the created AMD64 Store node
380 static ir_node *gen_Store(ir_node *node)
382 ir_node *block = be_transform_node(get_nodes_block(node));
383 ir_node *ptr = get_Store_ptr(node);
384 ir_node *new_ptr = be_transform_node(ptr);
385 ir_node *mem = get_Store_mem(node);
386 ir_node *new_mem = be_transform_node(mem);
387 ir_node *val = get_Store_value(node);
388 ir_node *new_val = be_transform_node(val);
389 ir_mode *mode = get_irn_mode(val);
390 dbg_info *dbgi = get_irn_dbg_info(node);
391 ir_node *new_store = NULL;
393 if (mode_is_float(mode)) {
394 panic("Float not supported yet");
396 assert(mode_is_data(mode) && "unsupported mode for Store");
397 new_store = new_bd_amd64_Store(dbgi, block, new_ptr, new_val, new_mem);
399 set_irn_pinned(new_store, get_irn_pinned(node));
406 * @return the created AMD64 Load node
408 static ir_node *gen_Load(ir_node *node)
410 ir_node *block = be_transform_node(get_nodes_block(node));
411 ir_node *ptr = get_Load_ptr(node);
412 ir_node *new_ptr = be_transform_node(ptr);
413 ir_node *mem = get_Load_mem(node);
414 ir_node *new_mem = be_transform_node(mem);
415 ir_mode *mode = get_Load_mode(node);
416 dbg_info *dbgi = get_irn_dbg_info(node);
417 ir_node *new_load = NULL;
419 if (mode_is_float(mode)) {
420 panic("Float not supported yet");
422 assert(mode_is_data(mode) && "unsupported mode for Load");
423 new_load = new_bd_amd64_Load(dbgi, block, new_ptr, new_mem);
425 set_irn_pinned(new_load, get_irn_pinned(node));
427 /* check for special case: the loaded value might not be used */
428 // if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
429 // /* add a result proj and a Keep to produce a pseudo use */
430 // ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_amd64_Load_res);
431 // be_new_Keep(block, 1, &proj);
438 * Transform a Proj from a Load.
440 static ir_node *gen_Proj_Load(ir_node *node)
442 ir_node *load = get_Proj_pred(node);
443 ir_node *new_load = be_transform_node(load);
444 dbg_info *dbgi = get_irn_dbg_info(node);
445 long proj = get_Proj_proj(node);
447 /* renumber the proj */
448 switch (get_amd64_irn_opcode(new_load)) {
450 /* handle all gp loads equal: they have the same proj numbers. */
451 if (proj == pn_Load_res) {
452 return new_rd_Proj(dbgi, new_load, mode_Lu, pn_amd64_Load_res);
453 } else if (proj == pn_Load_M) {
454 return new_rd_Proj(dbgi, new_load, mode_M, pn_amd64_Load_M);
458 case iro_sparc_fpaLoad:
459 panic("FP not implemented yet");
463 panic("Unsupported Proj from Load");
466 return be_duplicate_node(node);
470 * Transform a Proj node.
472 static ir_node *gen_Proj(ir_node *node)
474 ir_graph *irg = current_ir_graph;
475 dbg_info *dbgi = get_irn_dbg_info(node);
476 ir_node *pred = get_Proj_pred(node);
477 long proj = get_Proj_proj(node);
482 if (is_Store(pred)) {
483 if (proj == pn_Store_M) {
484 return be_transform_node(pred);
486 panic("Unsupported Proj from Store");
488 } else if (is_Load(pred)) {
489 return gen_Proj_Load(node);
490 // } else if (be_is_SubSP(pred)) {
491 // //panic("gen_Proj not implemented for SubSP");
492 // return gen_Proj_be_SubSP(node);
493 // } else if (be_is_AddSP(pred)) {
494 // //panic("gen_Proj not implemented for AddSP");
495 // return gen_Proj_be_AddSP(node);
496 // } else if (is_Cmp(pred)) {
497 // //panic("gen_Proj not implemented for Cmp");
498 // return gen_Proj_Cmp(node);
499 // } else if (is_Div(pred)) {
500 // return gen_Proj_Div(node);
501 } else if (is_Start(pred)) {
503 // if (proj == pn_Start_X_initial_exec) {
504 // ir_node *block = get_nodes_block(pred);
507 // // we exchange the ProjX with a jump
508 // block = be_transform_node(block);
509 // jump = new_rd_Jmp(dbgi, block);
513 // if (node == get_irg_anchor(irg, anchor_tls)) {
514 // return gen_Proj_tls(node);
518 // ir_node *new_pred = be_transform_node(pred);
519 // ir_mode *mode = get_irn_mode(node);
520 // if (mode_needs_gp_reg(mode)) {
521 // ir_node *new_proj = new_r_Proj(new_pred, mode_Iu, get_Proj_proj(node));
522 // new_proj->node_nr = node->node_nr;
527 return be_duplicate_node(node);
531 * Transforms a FrameAddr into an AMD64 Add.
533 static ir_node *gen_be_FrameAddr(ir_node *node)
535 ir_node *block = be_transform_node(get_nodes_block(node));
536 ir_entity *ent = be_get_frame_entity(node);
537 ir_node *fp = be_get_FrameAddr_frame(node);
538 ir_node *new_fp = be_transform_node(fp);
539 dbg_info *dbgi = get_irn_dbg_info(node);
542 new_node = new_bd_amd64_FrameAddr(dbgi, block, new_fp, ent);
546 /* Boilerplate code for transformation: */
548 static void amd64_pretransform_node(void)
550 amd64_code_gen_t *cg = env_cg;
553 // nomem = get_irg_no_mem(current_ir_graph);
556 static void set_transformer(ir_op *op, be_transform_func amd64_transform_func)
558 op->ops.generic = (op_func)amd64_transform_func;
561 static void amd64_register_transformers(void)
563 clear_irp_opcodes_generic_func();
565 set_transformer(op_Const, gen_Const);
566 set_transformer(op_SymConst, gen_SymConst);
567 set_transformer(op_Add, gen_Add);
568 set_transformer(op_Mul, gen_Mul);
569 set_transformer(op_be_Call, gen_be_Call);
570 set_transformer(op_be_FrameAddr, gen_be_FrameAddr);
571 set_transformer(op_Conv, gen_Conv);
572 set_transformer(op_Jmp, gen_Jmp);
573 set_transformer(op_Cmp, gen_Cmp);
574 set_transformer(op_Cond, gen_Cond);
575 set_transformer(op_Phi, gen_Phi);
576 set_transformer(op_Load, gen_Load);
577 set_transformer(op_Store, gen_Store);
578 set_transformer(op_Proj, gen_Proj);
582 void amd64_transform_graph(amd64_code_gen_t *cg)
584 amd64_register_transformers();
586 be_transform_graph(cg->irg, amd64_pretransform_node);
589 void amd64_init_transform(void)
591 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.transform");