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4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
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8 * Foundation and appearing in the file LICENSE.GPL included in the
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11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief code selection (transform FIRM into amd64 FIRM)
23 * @version $Id: amd64_transform.c 26673 2009-10-01 16:43:13Z matze $
28 #include "irgraph_t.h"
38 #include "../benode.h"
39 #include "../betranshlp.h"
40 #include "../beutil.h"
41 #include "bearch_amd64_t.h"
43 #include "amd64_nodes_attr.h"
44 #include "amd64_transform.h"
45 #include "amd64_new_nodes.h"
47 #include "gen_amd64_regalloc_if.h"
49 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
51 /** holds the current code generator during transformation */
52 static amd64_code_gen_t *env_cg;
54 ///* its enough to have those once */
55 //static ir_node *nomem, *noreg_GP;
57 /* Some support functions: */
59 static inline int mode_needs_gp_reg(ir_mode *mode)
61 return mode_is_int(mode) || mode_is_reference(mode);
65 * Create a DAG constructing a given Const.
67 * @param irn a Firm const
69 static ir_node *create_const_graph(ir_node *irn, ir_node *block)
71 tarval *tv = get_Const_tarval(irn);
72 ir_mode *mode = get_tarval_mode(tv);
73 dbg_info *dbgi = get_irn_dbg_info(irn);
76 if (mode_is_reference(mode)) {
77 /* AMD64 is 64bit, so we can safely convert a reference tarval into Iu */
78 assert(get_mode_size_bits(mode) == get_mode_size_bits(mode_Lu));
79 tv = tarval_convert_to(tv, mode_Lu);
82 value = get_tarval_long(tv);
83 //d// printf ("TEST GENERATE %d\n", value);
85 return new_bd_amd64_Immediate(dbgi, block, value);
88 /* Op transformers: */
91 * Transforms a Const node.
93 * @return The transformed AMD64 node.
95 static ir_node *gen_Const(ir_node *node) {
96 ir_node *block = be_transform_node(get_nodes_block(node));
97 ir_mode *mode = get_irn_mode(node);
98 ir_node *res = create_const_graph(node, block);
101 be_dep_on_frame(res);
107 * Transforms a SymConst node.
109 * @return The transformed ARM node.
111 static ir_node *gen_SymConst(ir_node *node)
113 ir_node *block = be_transform_node(get_nodes_block(node));
114 ir_entity *entity = get_SymConst_entity(node);
115 dbg_info *dbgi = get_irn_dbg_info(node);
118 new_node = new_bd_amd64_SymConst(dbgi, block, entity);
119 be_dep_on_frame(new_node);
124 * Transforms an Add node.
126 * @return The transformed AMD64 node.
128 static ir_node *gen_Add(ir_node *node) {
129 ir_node *block = be_transform_node(get_nodes_block(node));
130 /* ir_mode *mode = get_irn_mode(node); */
131 ir_node *op1 = get_Add_left(node);
132 ir_node *op2 = get_Add_right(node);
133 dbg_info *dbgi = get_irn_dbg_info(node);
134 ir_node *new_op1 = be_transform_node(op1);
135 ir_node *new_op2 = be_transform_node(op2);
137 ir_node *res = new_bd_amd64_Add(dbgi, block, new_op1, new_op2);
138 be_dep_on_frame (res);
143 * Transforms an Sub node.
145 * @return The transformed AMD64 node.
147 static ir_node *gen_Sub(ir_node *node) {
148 ir_node *block = be_transform_node(get_nodes_block(node));
149 /* ir_mode *mode = get_irn_mode(node); */
150 ir_node *op1 = get_Sub_left(node);
151 ir_node *op2 = get_Sub_right(node);
152 dbg_info *dbgi = get_irn_dbg_info(node);
153 ir_node *new_op1 = be_transform_node(op1);
154 ir_node *new_op2 = be_transform_node(op2);
156 ir_node *res = new_bd_amd64_Sub(dbgi, block, new_op1, new_op2);
157 be_dep_on_frame (res);
161 static ir_node *gen_Mul(ir_node *node) {
162 ir_node *block = be_transform_node(get_nodes_block(node));
163 /* ir_mode *mode = get_irn_mode(node); */
164 ir_node *op1 = get_Mul_left(node);
165 ir_node *op2 = get_Mul_right(node);
166 dbg_info *dbgi = get_irn_dbg_info(node);
167 ir_node *new_op1 = be_transform_node(op1);
168 ir_node *new_op2 = be_transform_node(op2);
170 ir_node *res = new_bd_amd64_Mul(dbgi, block, new_op1, new_op2);
171 be_dep_on_frame (res);
175 static ir_node *gen_Minus(ir_node *node)
177 ir_node *block = be_transform_node(get_nodes_block(node));
178 ir_node *val = be_transform_node(get_Minus_op(node));
179 dbg_info *dbgi = get_irn_dbg_info(node);
181 return new_bd_amd64_Neg(dbgi, block, val);
184 static ir_node *gen_Jmp(ir_node *node)
186 ir_node *block = get_nodes_block(node);
187 ir_node *new_block = be_transform_node(block);
188 dbg_info *dbgi = get_irn_dbg_info(node);
190 return new_bd_amd64_Jmp(dbgi, new_block);
193 static ir_node *gen_be_Call(ir_node *node)
195 ir_node *res = be_duplicate_node(node);
196 arch_irn_add_flags(res, arch_irn_flags_modify_flags);
201 static ir_node *gen_Cmp(ir_node *node)
203 ir_node *block = be_transform_node(get_nodes_block(node));
204 ir_node *op1 = get_Cmp_left(node);
205 ir_node *op2 = get_Cmp_right(node);
206 ir_mode *cmp_mode = get_irn_mode(op1);
207 dbg_info *dbgi = get_irn_dbg_info(node);
212 if (mode_is_float(cmp_mode)) {
213 panic("Floating point not implemented yet (in gen_Cmp)!");
216 assert(get_irn_mode(op2) == cmp_mode);
217 is_unsigned = !mode_is_signed(cmp_mode);
219 new_op1 = be_transform_node(op1);
220 // new_op1 = gen_extension(dbgi, block, new_op1, cmp_mode);
221 new_op2 = be_transform_node(op2);
222 // new_op2 = gen_extension(dbgi, block, new_op2, cmp_mode);
223 return new_bd_amd64_Cmp(dbgi, block, new_op1, new_op2, false,
230 * @return the created ARM Cond node
232 static ir_node *gen_Cond(ir_node *node)
234 ir_node *selector = get_Cond_selector(node);
235 ir_mode *mode = get_irn_mode(selector);
240 if (mode != mode_b) {
241 panic ("create_Switch not implemented yet!");
242 // return gen_SwitchJmp(node);
244 assert(is_Proj(selector));
246 block = be_transform_node(get_nodes_block(node));
247 dbgi = get_irn_dbg_info(node);
248 flag_node = be_transform_node(get_Proj_pred(selector));
250 return new_bd_amd64_Jcc(dbgi, block, flag_node, get_Proj_proj(selector));
254 // * Create an And that will zero out upper bits.
256 // * @param dbgi debug info
257 // * @param block the basic block
258 // * @param op the original node
259 // * param src_bits number of lower bits that will remain
261 //static ir_node *gen_zero_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
264 // if (src_bits == 8) {
265 // return new_bd_arm_And_imm(dbgi, block, op, 0xFF, 0);
266 // } else if (src_bits == 16) {
267 // ir_node *lshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, 16);
268 // ir_node *rshift = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift, ARM_SHF_LSR_IMM, 16);
271 // panic("zero extension only supported for 8 and 16 bits");
276 // * Generate code for a sign extension.
278 //static ir_node *gen_sign_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
281 // int shift_width = 32 - src_bits;
282 // ir_node *lshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, op, ARM_SHF_LSL_IMM, shift_width);
283 // ir_node *rshift_node = new_bd_arm_Mov_reg_shift_imm(dbgi, block, lshift_node, ARM_SHF_ASR_IMM, shift_width);
284 // return rshift_node;
287 //static ir_node *gen_extension(dbg_info *dbgi, ir_node *block, ir_node *op,
288 // ir_mode *orig_mode)
290 // int bits = get_mode_size_bits(orig_mode);
294 // if (mode_is_signed(orig_mode)) {
295 // return gen_sign_extension(dbgi, block, op, bits);
297 // return gen_zero_extension(dbgi, block, op, bits);
302 // * returns true if it is assured, that the upper bits of a node are "clean"
303 // * which means for a 16 or 8 bit value, that the upper bits in the register
304 // * are 0 for unsigned and a copy of the last significant bit for signed
307 //static bool upper_bits_clean(ir_node *transformed_node, ir_mode *mode)
309 // (void) transformed_node;
316 * Change some phi modes
318 static ir_node *gen_Phi(ir_node *node)
320 const arch_register_req_t *req;
321 ir_node *block = be_transform_node(get_nodes_block(node));
322 ir_graph *irg = current_ir_graph;
323 dbg_info *dbgi = get_irn_dbg_info(node);
324 ir_mode *mode = get_irn_mode(node);
327 if (mode_needs_gp_reg(mode)) {
328 /* all integer operations are on 64bit registers now */
330 req = amd64_reg_classes[CLASS_amd64_gp].class_req;
332 req = arch_no_register_req;
335 /* phi nodes allow loops, so we use the old arguments for now
336 * and fix this later */
337 phi = new_ir_node(dbgi, irg, block, op_Phi, mode, get_irn_arity(node),
338 get_irn_in(node) + 1);
339 copy_node_attr(irg, node, phi);
340 be_duplicate_deps(node, phi);
342 arch_set_out_register_req(phi, 0, req);
344 be_enqueue_preds(node);
352 * Transforms a Conv node.
354 * @return The created ia32 Conv node
356 static ir_node *gen_Conv(ir_node *node)
358 ir_node *block = be_transform_node(get_nodes_block(node));
359 ir_node *op = get_Conv_op(node);
360 ir_node *new_op = be_transform_node(op);
361 ir_mode *src_mode = get_irn_mode(op);
362 ir_mode *dst_mode = get_irn_mode(node);
363 dbg_info *dbgi = get_irn_dbg_info(node);
365 if (src_mode == dst_mode)
368 if (mode_is_float(src_mode) || mode_is_float(dst_mode)) {
369 panic("float not supported yet");
370 } else { /* complete in gp registers */
371 int src_bits = get_mode_size_bits(src_mode);
372 int dst_bits = get_mode_size_bits(dst_mode);
376 if (src_bits == dst_bits) {
377 /* kill unnecessary conv */
381 if (src_bits < dst_bits) {
390 return new_bd_amd64_Conv(dbgi, block, new_op, min_mode);
392 //if (upper_bits_clean(new_op, min_mode)) {
396 //if (mode_is_signed(min_mode)) {
397 // return gen_sign_extension(dbg, block, new_op, min_bits);
399 // return gen_zero_extension(dbg, block, new_op, min_bits);
405 * Transforms a Store.
407 * @return the created AMD64 Store node
409 static ir_node *gen_Store(ir_node *node)
411 ir_node *block = be_transform_node(get_nodes_block(node));
412 ir_node *ptr = get_Store_ptr(node);
413 ir_node *new_ptr = be_transform_node(ptr);
414 ir_node *mem = get_Store_mem(node);
415 ir_node *new_mem = be_transform_node(mem);
416 ir_node *val = get_Store_value(node);
417 ir_node *new_val = be_transform_node(val);
418 ir_mode *mode = get_irn_mode(val);
419 dbg_info *dbgi = get_irn_dbg_info(node);
420 ir_node *new_store = NULL;
422 if (mode_is_float(mode)) {
423 panic("Float not supported yet");
425 assert(mode_is_data(mode) && "unsupported mode for Store");
426 new_store = new_bd_amd64_Store(dbgi, block, new_ptr, new_val, new_mem, 0);
428 set_irn_pinned(new_store, get_irn_pinned(node));
435 * @return the created AMD64 Load node
437 static ir_node *gen_Load(ir_node *node)
439 ir_node *block = be_transform_node(get_nodes_block(node));
440 ir_node *ptr = get_Load_ptr(node);
441 ir_node *new_ptr = be_transform_node(ptr);
442 ir_node *mem = get_Load_mem(node);
443 ir_node *new_mem = be_transform_node(mem);
444 ir_mode *mode = get_Load_mode(node);
445 dbg_info *dbgi = get_irn_dbg_info(node);
446 ir_node *new_load = NULL;
448 if (mode_is_float(mode)) {
449 panic("Float not supported yet");
451 assert(mode_is_data(mode) && "unsupported mode for Load");
452 new_load = new_bd_amd64_Load(dbgi, block, new_ptr, new_mem, 0);
454 set_irn_pinned(new_load, get_irn_pinned(node));
456 /* check for special case: the loaded value might not be used */
457 // if (be_get_Proj_for_pn(node, pn_Load_res) == NULL) {
458 // /* add a result proj and a Keep to produce a pseudo use */
459 // ir_node *proj = new_r_Proj(new_load, mode_Iu, pn_amd64_Load_res);
460 // be_new_Keep(block, 1, &proj);
467 * Transform a Proj from a Load.
469 static ir_node *gen_Proj_Load(ir_node *node)
471 ir_node *load = get_Proj_pred(node);
472 ir_node *new_load = be_transform_node(load);
473 dbg_info *dbgi = get_irn_dbg_info(node);
474 long proj = get_Proj_proj(node);
476 /* renumber the proj */
477 switch (get_amd64_irn_opcode(new_load)) {
479 /* handle all gp loads equal: they have the same proj numbers. */
480 if (proj == pn_Load_res) {
481 return new_rd_Proj(dbgi, new_load, mode_Lu, pn_amd64_Load_res);
482 } else if (proj == pn_Load_M) {
483 return new_rd_Proj(dbgi, new_load, mode_M, pn_amd64_Load_M);
487 case iro_sparc_fpaLoad:
488 panic("FP not implemented yet");
492 panic("Unsupported Proj from Load");
495 return be_duplicate_node(node);
499 * Transform a Proj node.
501 static ir_node *gen_Proj(ir_node *node)
503 ir_graph *irg = current_ir_graph;
504 dbg_info *dbgi = get_irn_dbg_info(node);
505 ir_node *pred = get_Proj_pred(node);
506 long proj = get_Proj_proj(node);
511 if (is_Store(pred)) {
512 if (proj == pn_Store_M) {
513 return be_transform_node(pred);
515 panic("Unsupported Proj from Store");
517 } else if (is_Load(pred)) {
518 return gen_Proj_Load(node);
519 // } else if (be_is_SubSP(pred)) {
520 // //panic("gen_Proj not implemented for SubSP");
521 // return gen_Proj_be_SubSP(node);
522 // } else if (be_is_AddSP(pred)) {
523 // //panic("gen_Proj not implemented for AddSP");
524 // return gen_Proj_be_AddSP(node);
525 // } else if (is_Cmp(pred)) {
526 // //panic("gen_Proj not implemented for Cmp");
527 // return gen_Proj_Cmp(node);
528 // } else if (is_Div(pred)) {
529 // return gen_Proj_Div(node);
530 } else if (is_Start(pred)) {
532 // if (proj == pn_Start_X_initial_exec) {
533 // ir_node *block = get_nodes_block(pred);
536 // // we exchange the ProjX with a jump
537 // block = be_transform_node(block);
538 // jump = new_rd_Jmp(dbgi, block);
542 // if (node == get_irg_anchor(irg, anchor_tls)) {
543 // return gen_Proj_tls(node);
547 // ir_node *new_pred = be_transform_node(pred);
548 // ir_mode *mode = get_irn_mode(node);
549 // if (mode_needs_gp_reg(mode)) {
550 // ir_node *new_proj = new_r_Proj(new_pred, mode_Iu, get_Proj_proj(node));
551 // new_proj->node_nr = node->node_nr;
556 return be_duplicate_node(node);
560 * Transforms a FrameAddr into an AMD64 Add.
562 static ir_node *gen_be_FrameAddr(ir_node *node)
564 ir_node *block = be_transform_node(get_nodes_block(node));
565 ir_entity *ent = be_get_frame_entity(node);
566 ir_node *fp = be_get_FrameAddr_frame(node);
567 ir_node *new_fp = be_transform_node(fp);
568 dbg_info *dbgi = get_irn_dbg_info(node);
571 new_node = new_bd_amd64_FrameAddr(dbgi, block, new_fp, ent);
575 /* Boilerplate code for transformation: */
577 static void amd64_pretransform_node(void)
579 amd64_code_gen_t *cg = env_cg;
582 // nomem = get_irg_no_mem(current_ir_graph);
585 static void amd64_register_transformers(void)
587 be_start_transform_setup();
589 be_set_transform_function(op_Const, gen_Const);
590 be_set_transform_function(op_SymConst, gen_SymConst);
591 be_set_transform_function(op_Add, gen_Add);
592 be_set_transform_function(op_Sub, gen_Sub);
593 be_set_transform_function(op_Mul, gen_Mul);
594 be_set_transform_function(op_be_Call, gen_be_Call);
595 be_set_transform_function(op_be_FrameAddr, gen_be_FrameAddr);
596 be_set_transform_function(op_Conv, gen_Conv);
597 be_set_transform_function(op_Jmp, gen_Jmp);
598 be_set_transform_function(op_Cmp, gen_Cmp);
599 be_set_transform_function(op_Cond, gen_Cond);
600 be_set_transform_function(op_Phi, gen_Phi);
601 be_set_transform_function(op_Load, gen_Load);
602 be_set_transform_function(op_Store, gen_Store);
603 be_set_transform_function(op_Proj, gen_Proj);
604 be_set_transform_function(op_Minus, gen_Minus);
608 void amd64_transform_graph(amd64_code_gen_t *cg)
610 amd64_register_transformers();
612 be_transform_graph(cg->irg, amd64_pretransform_node);
615 void amd64_init_transform(void)
617 FIRM_DBG_REGISTER(dbg, "firm.be.amd64.transform");