2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief emit assembler for a backend graph
42 #include "beblocksched.h"
44 #include "amd64_emitter.h"
45 #include "gen_amd64_emitter.h"
46 #include "gen_amd64_regalloc_if.h"
47 #include "amd64_nodes_attr.h"
48 #include "amd64_new_nodes.h"
52 /*************************************************************
54 * (_) | | / _| | | | |
55 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
56 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
57 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
58 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
61 *************************************************************/
64 * Returns the target block for a control flow node.
66 static ir_node *get_cfop_target_block(const ir_node *irn)
68 return (ir_node*)get_irn_link(irn);
71 void amd64_emitf(ir_node const *const node, char const *fmt, ...)
78 char const *start = fmt;
80 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
83 be_emit_string_len(start, fmt - start);
100 arch_register_t const *reg;
107 amd64_attr_t const *const attr = get_amd64_attr_const(node);
108 be_emit_irprintf("$0x%X", attr->ext.imm_value);
113 if (*fmt < '0' || '9' <= *fmt)
115 reg = arch_get_irn_register_out(node, *fmt++ - '0');
119 ir_entity const *const ent = va_arg(ap, ir_entity const*);
120 be_gas_emit_entity(ent);
125 ir_node *const block = get_cfop_target_block(node);
126 be_gas_emit_block_name(block);
131 amd64_SymConst_attr_t const *const attr = get_amd64_SymConst_attr_const(node);
133 be_emit_irprintf("%d", attr->fp_offset);
138 reg = va_arg(ap, arch_register_t const*);
141 be_emit_string(reg->name);
146 if ('0' <= *fmt && *fmt <= '9') {
148 } else if (*fmt == '*') {
150 pos = va_arg(ap, int);
154 reg = arch_get_irn_register_in(node, pos);
159 int const num = va_arg(ap, int);
160 be_emit_irprintf("%d", num);
165 char const *const str = va_arg(ap, char const*);
171 unsigned const num = va_arg(ap, unsigned);
172 be_emit_irprintf("%u", num);
178 panic("unknown format conversion");
182 be_emit_finish_line_gas(node);
186 /***********************************************************************************
189 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
190 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
191 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
192 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
194 ***********************************************************************************/
199 static void emit_amd64_SymConst(const ir_node *irn)
201 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(irn);
202 amd64_emitf(irn, "mov $%E, %D0", attr->entity);
208 static void emit_amd64_Conv(const ir_node *irn)
210 amd64_emitf(irn, "mov %S0, %D0");
215 * Returns the next block in a block schedule.
217 static ir_node *sched_next_block(const ir_node *block)
219 return (ir_node*)get_irn_link(block);
225 static void emit_amd64_Jmp(const ir_node *node)
227 ir_node *block, *next_block;
229 /* for now, the code works for scheduled and non-schedules blocks */
230 block = get_nodes_block(node);
232 /* we have a block schedule */
233 next_block = sched_next_block(block);
234 if (get_cfop_target_block(node) != next_block) {
235 amd64_emitf(node, "jmp %L");
236 } else if (be_options.verbose_asm) {
237 amd64_emitf(node, "/* fallthrough to %L */");
242 * Emit a Compare with conditional branch.
244 static void emit_amd64_Jcc(const ir_node *irn)
246 const ir_node *proj_true = NULL;
247 const ir_node *proj_false = NULL;
248 const ir_node *block;
249 const ir_node *next_block;
251 const amd64_attr_t *attr = get_amd64_attr_const(irn);
252 ir_relation relation = attr->ext.relation;
253 ir_node *op1 = get_irn_n(irn, 0);
254 const amd64_attr_t *cmp_attr = get_amd64_attr_const(op1);
255 bool is_signed = !cmp_attr->data.cmp_unsigned;
257 assert(is_amd64_Cmp(op1));
259 foreach_out_edge(irn, edge) {
260 ir_node *proj = get_edge_src_irn(edge);
261 long nr = get_Proj_proj(proj);
262 if (nr == pn_Cond_true) {
269 if (cmp_attr->data.ins_permuted) {
270 relation = get_inversed_relation(relation);
273 /* for now, the code works for scheduled and non-schedules blocks */
274 block = get_nodes_block(irn);
276 /* we have a block schedule */
277 next_block = sched_next_block(block);
279 assert(relation != ir_relation_false);
280 assert(relation != ir_relation_true);
282 if (get_cfop_target_block(proj_true) == next_block) {
283 /* exchange both proj's so the second one can be omitted */
284 const ir_node *t = proj_true;
286 proj_true = proj_false;
288 relation = get_negated_relation(relation);
291 switch (relation & ir_relation_less_equal_greater) {
292 case ir_relation_equal: suffix = "e"; break;
293 case ir_relation_less: suffix = is_signed ? "l" : "b"; break;
294 case ir_relation_less_equal: suffix = is_signed ? "le" : "be"; break;
295 case ir_relation_greater: suffix = is_signed ? "g" : "a"; break;
296 case ir_relation_greater_equal: suffix = is_signed ? "ge" : "ae"; break;
297 case ir_relation_less_greater: suffix = "ne"; break;
298 case ir_relation_less_equal_greater: suffix = "mp"; break;
299 default: panic("Cmp has unsupported pnc");
302 /* emit the true proj */
303 amd64_emitf(proj_true, "j%s %L", suffix);
305 if (get_cfop_target_block(proj_false) != next_block) {
306 amd64_emitf(proj_false, "jmp %L");
307 } else if (be_options.verbose_asm) {
308 amd64_emitf(proj_false, "/* fallthrough to %L */");
313 * Emits code for a call.
315 static void emit_be_Call(const ir_node *node)
317 ir_entity *entity = be_Call_get_entity(node);
319 /* %eax/%rax is used in AMD64 to pass the number of vector parameters for
320 * variable argument counts */
321 if (get_method_variadicity (be_Call_get_type((ir_node *) node))) {
322 /* But this still is a hack... */
323 amd64_emitf(node, "xor %%rax, %%rax");
327 amd64_emitf(node, "call %E", entity);
329 be_emit_pad_comment();
330 be_emit_cstring("/* FIXME: call NULL entity?! */\n");
337 static void emit_be_Copy(const ir_node *irn)
339 ir_mode *mode = get_irn_mode(irn);
341 if (arch_get_irn_register_in(irn, 0) == arch_get_irn_register_out(irn, 0)) {
346 if (mode_is_float(mode)) {
347 panic("move not supported for FP");
348 } else if (mode_is_data(mode)) {
349 amd64_emitf(irn, "mov %S0, %D0");
351 panic("move not supported for this mode");
355 static void emit_be_Perm(const ir_node *node)
357 const arch_register_t *in0, *in1;
359 in0 = arch_get_irn_register(get_irn_n(node, 0));
360 in1 = arch_get_irn_register(get_irn_n(node, 1));
362 arch_register_class_t const* const cls0 = in0->reg_class;
363 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
365 amd64_emitf(node, "xchg %R, %R", in0, in1);
367 if (cls0 != &amd64_reg_classes[CLASS_amd64_gp]) {
368 panic("unexpected register class in be_Perm (%+F)", node);
372 static void emit_amd64_FrameAddr(const ir_node *irn)
374 const amd64_SymConst_attr_t *attr =
375 (const amd64_SymConst_attr_t*) get_amd64_attr_const(irn);
377 amd64_emitf(irn, "mov %S0, %D0");
378 amd64_emitf(irn, "add $%u, %D0", attr->fp_offset);
382 * Emits code to increase stack pointer.
384 static void emit_be_IncSP(const ir_node *node)
386 int offs = be_get_IncSP_offset(node);
392 amd64_emitf(node, "sub, $%d, %D0", offs);
394 amd64_emitf(node, "add, $%d, %D0", -offs);
399 * Emits code for a return.
401 static void emit_be_Return(const ir_node *node)
403 be_emit_cstring("\tret");
404 be_emit_finish_line_gas(node);
408 static void emit_amd64_binop_op(const ir_node *irn, int second_op)
410 if (irn->op == op_amd64_Add) {
411 amd64_emitf(irn, "add %S*, %D0", second_op);
412 } else if (irn->op == op_amd64_Sub) {
413 amd64_emitf(irn, "neg %S*", second_op);
414 amd64_emitf(irn, "add %S*, %D0", second_op);
415 amd64_emitf(irn, "neg %S*", second_op);
421 * Emits an arithmetic operation that handles arbitraty input registers.
423 static void emit_amd64_binop(const ir_node *irn)
425 const arch_register_t *reg_s1 = arch_get_irn_register_in(irn, 0);
426 const arch_register_t *reg_s2 = arch_get_irn_register_in(irn, 1);
427 const arch_register_t *reg_d1 = arch_get_irn_register_out(irn, 0);
431 if (reg_d1 != reg_s1 && reg_d1 != reg_s2) {
432 amd64_emitf(irn, "mov %R, %R", reg_s1, reg_d1);
434 } else if (reg_d1 == reg_s2 && reg_d1 != reg_s1) {
438 emit_amd64_binop_op(irn, second_op);
442 * Enters the emitter functions for handled nodes into the generic
443 * pointer of an opcode.
445 static void amd64_register_emitters(void)
447 /* first clear the generic function pointer for all ops */
448 ir_clear_opcodes_generic_func();
450 /* register all emitter functions defined in spec */
451 amd64_register_spec_emitters();
453 be_set_emitter(op_amd64_Add, emit_amd64_binop);
454 be_set_emitter(op_amd64_Conv, emit_amd64_Conv);
455 be_set_emitter(op_amd64_FrameAddr, emit_amd64_FrameAddr);
456 be_set_emitter(op_amd64_Jcc, emit_amd64_Jcc);
457 be_set_emitter(op_amd64_Jmp, emit_amd64_Jmp);
458 be_set_emitter(op_amd64_Sub, emit_amd64_binop);
459 be_set_emitter(op_amd64_SymConst, emit_amd64_SymConst);
460 be_set_emitter(op_be_Call, emit_be_Call);
461 be_set_emitter(op_be_Copy, emit_be_Copy);
462 be_set_emitter(op_be_IncSP, emit_be_IncSP);
463 be_set_emitter(op_be_Perm, emit_be_Perm);
464 be_set_emitter(op_be_Return, emit_be_Return);
466 be_set_emitter(op_Phi, be_emit_nothing);
467 be_set_emitter(op_be_Keep, be_emit_nothing);
468 be_set_emitter(op_be_Start, be_emit_nothing);
472 * Walks over the nodes in a block connected by scheduling edges
473 * and emits code for each node.
475 static void amd64_gen_block(ir_node *block, void *data)
479 if (! is_Block(block))
482 be_gas_begin_block(block, true);
484 sched_foreach(block, node) {
491 * Sets labels for control flow nodes (jump target)
492 * TODO: Jump optimization
494 static void amd64_gen_labels(ir_node *block, void *env)
497 int n = get_Block_n_cfgpreds(block);
500 for (n--; n >= 0; n--) {
501 pred = get_Block_cfgpred(block, n);
502 set_irn_link(pred, block);
509 void amd64_gen_routine(ir_graph *irg)
511 ir_entity *entity = get_irg_entity(irg);
515 /* register all emitter functions */
516 amd64_register_emitters();
518 blk_sched = be_create_block_schedule(irg);
520 be_gas_emit_function_prolog(entity, 4, NULL);
522 irg_block_walk_graph(irg, amd64_gen_labels, NULL, NULL);
524 n = ARR_LEN(blk_sched);
525 for (i = 0; i < n; i++) {
526 ir_node *block = blk_sched[i];
527 ir_node *next = (i + 1) < n ? blk_sched[i+1] : NULL;
529 set_irn_link(block, next);
532 for (i = 0; i < n; ++i) {
533 ir_node *block = blk_sched[i];
535 amd64_gen_block(block, 0);
538 be_gas_emit_function_epilog(entity);