2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief emit assembler for a backend graph
42 #include "beblocksched.h"
44 #include "amd64_emitter.h"
45 #include "gen_amd64_emitter.h"
46 #include "gen_amd64_regalloc_if.h"
47 #include "amd64_nodes_attr.h"
48 #include "amd64_new_nodes.h"
52 /*************************************************************
54 * (_) | | / _| | | | |
55 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
56 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
57 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
58 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
61 *************************************************************/
64 * Returns the target block for a control flow node.
66 static ir_node *get_cfop_target_block(const ir_node *irn)
68 return (ir_node*)get_irn_link(irn);
71 void amd64_emitf(ir_node const *const node, char const *fmt, ...)
78 char const *start = fmt;
80 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
83 be_emit_string_len(start, fmt - start);
100 arch_register_t const *reg;
107 amd64_attr_t const *const attr = get_amd64_attr_const(node);
108 be_emit_irprintf("$0x%X", attr->ext.imm_value);
113 if (*fmt < '0' || '9' <= *fmt)
115 reg = arch_get_irn_register_out(node, *fmt++ - '0');
119 ir_entity const *const ent = va_arg(ap, ir_entity const*);
120 be_gas_emit_entity(ent);
125 ir_node *const block = get_cfop_target_block(node);
126 be_gas_emit_block_name(block);
131 amd64_SymConst_attr_t const *const attr = get_amd64_SymConst_attr_const(node);
133 be_emit_irprintf("%d", attr->fp_offset);
138 reg = va_arg(ap, arch_register_t const*);
141 be_emit_string(reg->name);
146 if ('0' <= *fmt && *fmt <= '9') {
148 } else if (*fmt == '*') {
150 pos = va_arg(ap, int);
154 reg = arch_get_irn_register_in(node, pos);
159 int const num = va_arg(ap, int);
160 be_emit_irprintf("%d", num);
165 char const *const str = va_arg(ap, char const*);
171 unsigned const num = va_arg(ap, unsigned);
172 be_emit_irprintf("%u", num);
178 panic("unknown format conversion");
182 be_emit_finish_line_gas(node);
186 /***********************************************************************************
189 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
190 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
191 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
192 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
194 ***********************************************************************************/
197 * Default emitter for anything that we don't want to generate code for.
199 static void emit_nothing(const ir_node *node)
207 static void emit_amd64_SymConst(const ir_node *irn)
209 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(irn);
211 sym_or_tv_t key, *entry;
214 key.u.id = get_entity_ld_ident(attr->entity);
217 entry = set_insert(sym_or_tv_t, sym_or_tv, &key, sizeof(key), hash_ptr(key.u.generic));
218 if (entry->label == 0) {
219 /* allocate a label */
220 entry->label = get_unique_label();
222 label = entry->label;
225 amd64_emitf(irn, "mov $%E, %D0", attr->entity);
231 static void emit_amd64_Conv(const ir_node *irn)
233 amd64_emitf(irn, "mov %S0, %D0");
238 * Returns the next block in a block schedule.
240 static ir_node *sched_next_block(const ir_node *block)
242 return (ir_node*)get_irn_link(block);
248 static void emit_amd64_Jmp(const ir_node *node)
250 ir_node *block, *next_block;
252 /* for now, the code works for scheduled and non-schedules blocks */
253 block = get_nodes_block(node);
255 /* we have a block schedule */
256 next_block = sched_next_block(block);
257 if (get_cfop_target_block(node) != next_block) {
258 amd64_emitf(node, "jmp %L");
259 } else if (be_options.verbose_asm) {
260 amd64_emitf(node, "/* fallthrough to %L */");
265 * Emit a Compare with conditional branch.
267 static void emit_amd64_Jcc(const ir_node *irn)
269 const ir_node *proj_true = NULL;
270 const ir_node *proj_false = NULL;
271 const ir_node *block;
272 const ir_node *next_block;
274 const amd64_attr_t *attr = get_amd64_attr_const(irn);
275 ir_relation relation = attr->ext.relation;
276 ir_node *op1 = get_irn_n(irn, 0);
277 const amd64_attr_t *cmp_attr = get_amd64_attr_const(op1);
278 bool is_signed = !cmp_attr->data.cmp_unsigned;
280 assert(is_amd64_Cmp(op1));
282 foreach_out_edge(irn, edge) {
283 ir_node *proj = get_edge_src_irn(edge);
284 long nr = get_Proj_proj(proj);
285 if (nr == pn_Cond_true) {
292 if (cmp_attr->data.ins_permuted) {
293 relation = get_inversed_relation(relation);
296 /* for now, the code works for scheduled and non-schedules blocks */
297 block = get_nodes_block(irn);
299 /* we have a block schedule */
300 next_block = sched_next_block(block);
302 assert(relation != ir_relation_false);
303 assert(relation != ir_relation_true);
305 if (get_cfop_target_block(proj_true) == next_block) {
306 /* exchange both proj's so the second one can be omitted */
307 const ir_node *t = proj_true;
309 proj_true = proj_false;
311 relation = get_negated_relation(relation);
314 switch (relation & ir_relation_less_equal_greater) {
315 case ir_relation_equal: suffix = "e"; break;
316 case ir_relation_less: suffix = is_signed ? "l" : "b"; break;
317 case ir_relation_less_equal: suffix = is_signed ? "le" : "be"; break;
318 case ir_relation_greater: suffix = is_signed ? "g" : "a"; break;
319 case ir_relation_greater_equal: suffix = is_signed ? "ge" : "ae"; break;
320 case ir_relation_less_greater: suffix = "ne"; break;
321 case ir_relation_less_equal_greater: suffix = "mp"; break;
322 default: panic("Cmp has unsupported pnc");
325 /* emit the true proj */
326 amd64_emitf(proj_true, "j%s %L", suffix);
328 if (get_cfop_target_block(proj_false) != next_block) {
329 amd64_emitf(proj_false, "jmp %L");
330 } else if (be_options.verbose_asm) {
331 amd64_emitf(proj_false, "/* fallthrough to %L */");
336 * Emits code for a call.
338 static void emit_be_Call(const ir_node *node)
340 ir_entity *entity = be_Call_get_entity(node);
342 /* %eax/%rax is used in AMD64 to pass the number of vector parameters for
343 * variable argument counts */
344 if (get_method_variadicity (be_Call_get_type((ir_node *) node))) {
345 /* But this still is a hack... */
346 amd64_emitf(node, "xor %%rax, %%rax");
350 amd64_emitf(node, "call %E", entity);
352 be_emit_pad_comment();
353 be_emit_cstring("/* FIXME: call NULL entity?! */\n");
360 static void emit_be_Copy(const ir_node *irn)
362 ir_mode *mode = get_irn_mode(irn);
364 if (arch_get_irn_register_in(irn, 0) == arch_get_irn_register_out(irn, 0)) {
369 if (mode_is_float(mode)) {
370 panic("move not supported for FP");
371 } else if (mode_is_data(mode)) {
372 amd64_emitf(irn, "mov %S0, %D0");
374 panic("move not supported for this mode");
378 static void emit_be_Perm(const ir_node *node)
380 const arch_register_t *in0, *in1;
382 in0 = arch_get_irn_register(get_irn_n(node, 0));
383 in1 = arch_get_irn_register(get_irn_n(node, 1));
385 arch_register_class_t const* const cls0 = in0->reg_class;
386 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
388 amd64_emitf(node, "xchg %R, %R", in0, in1);
390 if (cls0 != &amd64_reg_classes[CLASS_amd64_gp]) {
391 panic("unexpected register class in be_Perm (%+F)", node);
395 static void emit_amd64_FrameAddr(const ir_node *irn)
397 const amd64_SymConst_attr_t *attr =
398 (const amd64_SymConst_attr_t*) get_amd64_attr_const(irn);
400 amd64_emitf(irn, "mov %S0, %D0");
401 amd64_emitf(irn, "add $%u, %D0", attr->fp_offset);
405 * Emits code to increase stack pointer.
407 static void emit_be_IncSP(const ir_node *node)
409 int offs = be_get_IncSP_offset(node);
415 amd64_emitf(node, "sub, $%d, %D0", offs);
417 amd64_emitf(node, "add, $%d, %D0", -offs);
422 * Emits code for a return.
424 static void emit_be_Return(const ir_node *node)
426 be_emit_cstring("\tret");
427 be_emit_finish_line_gas(node);
431 static void emit_amd64_binop_op(const ir_node *irn, int second_op)
433 if (irn->op == op_amd64_Add) {
434 amd64_emitf(irn, "add %S*, %D0", second_op);
435 } else if (irn->op == op_amd64_Sub) {
436 amd64_emitf(irn, "neg %S*", second_op);
437 amd64_emitf(irn, "add %S*, %D0", second_op);
438 amd64_emitf(irn, "neg %S*", second_op);
444 * Emits an arithmetic operation that handles arbitraty input registers.
446 static void emit_amd64_binop(const ir_node *irn)
448 const arch_register_t *reg_s1 = arch_get_irn_register_in(irn, 0);
449 const arch_register_t *reg_s2 = arch_get_irn_register_in(irn, 1);
450 const arch_register_t *reg_d1 = arch_get_irn_register_out(irn, 0);
454 if (reg_d1 != reg_s1 && reg_d1 != reg_s2) {
455 amd64_emitf(irn, "mov %R, %R", reg_s1, reg_d1);
457 } else if (reg_d1 == reg_s2 && reg_d1 != reg_s1) {
461 emit_amd64_binop_op(irn, second_op);
465 * The type of a emitter function.
467 typedef void (emit_func)(const ir_node *irn);
470 * Set a node emitter. Make it a bit more type safe.
472 static inline void set_emitter(ir_op *op, emit_func arm_emit_node)
474 op->ops.generic = (op_func)arm_emit_node;
478 * Enters the emitter functions for handled nodes into the generic
479 * pointer of an opcode.
481 static void amd64_register_emitters(void)
483 /* first clear the generic function pointer for all ops */
484 ir_clear_opcodes_generic_func();
486 /* register all emitter functions defined in spec */
487 amd64_register_spec_emitters();
489 set_emitter(op_amd64_SymConst, emit_amd64_SymConst);
490 set_emitter(op_amd64_Jmp, emit_amd64_Jmp);
491 set_emitter(op_amd64_Jcc, emit_amd64_Jcc);
492 set_emitter(op_amd64_Conv, emit_amd64_Conv);
493 set_emitter(op_amd64_FrameAddr, emit_amd64_FrameAddr);
494 set_emitter(op_be_Return, emit_be_Return);
495 set_emitter(op_be_Call, emit_be_Call);
496 set_emitter(op_be_Copy, emit_be_Copy);
497 set_emitter(op_be_IncSP, emit_be_IncSP);
498 set_emitter(op_be_Perm, emit_be_Perm);
500 set_emitter(op_amd64_Add, emit_amd64_binop);
501 set_emitter(op_amd64_Sub, emit_amd64_binop);
503 set_emitter(op_be_Start, emit_nothing);
504 set_emitter(op_be_Keep, emit_nothing);
505 set_emitter(op_Phi, emit_nothing);
508 typedef void (*emit_func_ptr) (const ir_node *);
511 * Emits code for a node.
513 static void amd64_emit_node(const ir_node *node)
515 ir_op *op = get_irn_op(node);
517 if (op->ops.generic) {
518 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
521 ir_fprintf(stderr, "No emitter for node %+F\n", node);
526 * Walks over the nodes in a block connected by scheduling edges
527 * and emits code for each node.
529 static void amd64_gen_block(ir_node *block, void *data)
533 if (! is_Block(block))
536 be_gas_begin_block(block, true);
538 sched_foreach(block, node) {
539 amd64_emit_node(node);
545 * Sets labels for control flow nodes (jump target)
546 * TODO: Jump optimization
548 static void amd64_gen_labels(ir_node *block, void *env)
551 int n = get_Block_n_cfgpreds(block);
554 for (n--; n >= 0; n--) {
555 pred = get_Block_cfgpred(block, n);
556 set_irn_link(pred, block);
563 void amd64_gen_routine(ir_graph *irg)
565 ir_entity *entity = get_irg_entity(irg);
569 /* register all emitter functions */
570 amd64_register_emitters();
572 blk_sched = be_create_block_schedule(irg);
574 be_gas_emit_function_prolog(entity, 4, NULL);
576 irg_block_walk_graph(irg, amd64_gen_labels, NULL, NULL);
578 n = ARR_LEN(blk_sched);
579 for (i = 0; i < n; i++) {
580 ir_node *block = blk_sched[i];
581 ir_node *next = (i + 1) < n ? blk_sched[i+1] : NULL;
583 set_irn_link(block, next);
586 for (i = 0; i < n; ++i) {
587 ir_node *block = blk_sched[i];
589 amd64_gen_block(block, 0);
592 be_gas_emit_function_epilog(entity);