2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief emit assembler for a backend graph
23 * @version $Id: amd64_emitter.c 26746 2009-11-27 08:53:15Z matze $
39 #include "../besched.h"
40 #include "../begnuas.h"
41 #include "../beblocksched.h"
42 #include "../be_dbgout.h"
44 #include "amd64_emitter.h"
45 #include "gen_amd64_emitter.h"
46 #include "gen_amd64_regalloc_if.h"
47 #include "amd64_nodes_attr.h"
48 #include "amd64_new_nodes.h"
50 #define SNPRINTF_BUF_LEN 128
52 #include "../benode.h"
55 * Returns the register at in position pos.
57 static const arch_register_t *get_in_reg(const ir_node *node, int pos)
60 const arch_register_t *reg = NULL;
62 assert(get_irn_arity(node) > pos && "Invalid IN position");
64 /* The out register of the operator at position pos is the
65 in register we need. */
66 op = get_irn_n(node, pos);
68 reg = arch_get_irn_register(op);
70 assert(reg && "no in register found");
75 * Returns the register at out position pos.
77 static const arch_register_t *get_out_reg(const ir_node *node, int pos)
80 const arch_register_t *reg = NULL;
82 /* 1st case: irn is not of mode_T, so it has only */
83 /* one OUT register -> good */
84 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
85 /* Proj with the corresponding projnum for the register */
87 if (get_irn_mode(node) != mode_T) {
88 reg = arch_get_irn_register(node);
89 } else if (is_amd64_irn(node)) {
90 reg = arch_irn_get_register(node, pos);
92 const ir_edge_t *edge;
94 foreach_out_edge(node, edge) {
95 proj = get_edge_src_irn(edge);
96 assert(is_Proj(proj) && "non-Proj from mode_T node");
97 if (get_Proj_proj(proj) == pos) {
98 reg = arch_get_irn_register(proj);
104 assert(reg && "no out register found");
108 /*************************************************************
110 * (_) | | / _| | | | |
111 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
112 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
113 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
114 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
117 *************************************************************/
119 void amd64_emit_register(const arch_register_t *reg)
122 be_emit_string(arch_register_get_name(reg));
125 void amd64_emit_immediate(const ir_node *node)
127 const amd64_attr_t *attr = get_amd64_attr_const (node);
129 be_emit_irprintf("0x%X", attr->ext.imm_value);
132 void amd64_emit_fp_offset(const ir_node *node)
134 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(node);
136 be_emit_irprintf("%d", attr->fp_offset);
139 void amd64_emit_source_register(const ir_node *node, int pos)
141 amd64_emit_register(get_in_reg(node, pos));
144 void amd64_emit_dest_register(const ir_node *node, int pos)
146 amd64_emit_register(get_out_reg(node, pos));
150 * Returns the target label for a control flow node.
153 static void amd64_emit_cfop_target(const ir_node *node)
155 ir_node *block = get_irn_link(node);
157 be_emit_irprintf("BLOCK_%ld", get_irn_node_nr(block));
161 /***********************************************************************************
164 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
165 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
166 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
167 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
169 ***********************************************************************************/
172 * Default emitter for anything that we don't want to generate code for.
174 static void emit_nothing(const ir_node *node)
182 static void emit_amd64_SymConst(const ir_node *irn)
184 const amd64_SymConst_attr_t *attr = get_amd64_SymConst_attr_const(irn);
186 sym_or_tv_t key, *entry;
189 key.u.id = get_entity_ld_ident(attr->entity);
192 entry = (sym_or_tv_t *)set_insert(sym_or_tv, &key, sizeof(key), HASH_PTR(key.u.generic));
193 if (entry->label == 0) {
194 /* allocate a label */
195 entry->label = get_unique_label();
197 label = entry->label;
200 be_emit_cstring("\tmov $");
201 be_gas_emit_entity(attr->entity);
202 be_emit_cstring(", ");
203 amd64_emit_dest_register(irn, 0);
204 be_emit_finish_line_gas(irn);
210 static void emit_amd64_Conv(const ir_node *irn)
212 const amd64_attr_t *attr = get_irn_generic_attr_const(irn);
215 be_emit_cstring("\tmov ");
216 amd64_emit_source_register(irn, 0);
217 be_emit_cstring(", ");
218 amd64_emit_dest_register(irn, 0);
219 be_emit_finish_line_gas(irn);
224 * Returns the next block in a block schedule.
226 static ir_node *sched_next_block(const ir_node *block)
228 return get_irn_link(block);
232 * Returns the target block for a control flow node.
234 static ir_node *get_cfop_target_block(const ir_node *irn)
236 return get_irn_link(irn);
240 * Emit the target label for a control flow node.
242 static void amd64_emit_cfop_target(const ir_node *irn)
244 ir_node *block = get_cfop_target_block(irn);
246 be_gas_emit_block_name(block);
252 static void emit_amd64_Jmp(const ir_node *node)
254 ir_node *block, *next_block;
256 /* for now, the code works for scheduled and non-schedules blocks */
257 block = get_nodes_block(node);
259 /* we have a block schedule */
260 next_block = sched_next_block(block);
261 if (get_cfop_target_block(node) != next_block) {
262 be_emit_cstring("\tjmp ");
263 amd64_emit_cfop_target(node);
265 be_emit_cstring("\t/* fallthrough to ");
266 amd64_emit_cfop_target(node);
267 be_emit_cstring(" */");
269 be_emit_finish_line_gas(node);
273 * Emit a Compare with conditional branch.
275 static void emit_amd64_Jcc(const ir_node *irn)
277 const ir_edge_t *edge;
278 const ir_node *proj_true = NULL;
279 const ir_node *proj_false = NULL;
280 const ir_node *block;
281 const ir_node *next_block;
283 const amd64_attr_t *attr = get_irn_generic_attr_const(irn);
284 int proj_num = attr->ext.pnc;
285 ir_node *op1 = get_irn_n(irn, 0);
286 const amd64_attr_t *cmp_attr = get_irn_generic_attr_const(op1);
287 bool is_signed = !cmp_attr->data.cmp_unsigned;
289 assert(is_amd64_Cmp(op1));
291 foreach_out_edge(irn, edge) {
292 ir_node *proj = get_edge_src_irn(edge);
293 long nr = get_Proj_proj(proj);
294 if (nr == pn_Cond_true) {
301 if (cmp_attr->data.ins_permuted) {
302 proj_num = get_mirrored_pnc(proj_num);
305 /* for now, the code works for scheduled and non-schedules blocks */
306 block = get_nodes_block(irn);
308 /* we have a block schedule */
309 next_block = sched_next_block(block);
311 assert(proj_num != pn_Cmp_False);
312 assert(proj_num != pn_Cmp_True);
314 if (get_cfop_target_block(proj_true) == next_block) {
315 /* exchange both proj's so the second one can be omitted */
316 const ir_node *t = proj_true;
318 proj_true = proj_false;
320 proj_num = get_negated_pnc(proj_num, mode_Lu);
324 case pn_Cmp_Eq: suffix = "e"; break;
325 case pn_Cmp_Lt: suffix = is_signed ? "l" : "b"; break;
326 case pn_Cmp_Le: suffix = is_signed ? "le" : "be"; break;
327 case pn_Cmp_Gt: suffix = is_signed ? "g" : "a"; break;
328 case pn_Cmp_Ge: suffix = is_signed ? "ge" : "ae"; break;
329 case pn_Cmp_Lg: suffix = "ne"; break;
330 case pn_Cmp_Leg: suffix = "mp"; break;
331 default: panic("Cmp has unsupported pnc");
334 /* emit the true proj */
335 be_emit_irprintf("\tj%s ", suffix);
336 amd64_emit_cfop_target(proj_true);
337 be_emit_finish_line_gas(proj_true);
339 if (get_cfop_target_block(proj_false) == next_block) {
340 be_emit_cstring("\t/* fallthrough to ");
341 amd64_emit_cfop_target(proj_false);
342 be_emit_cstring(" */");
343 be_emit_finish_line_gas(proj_false);
345 be_emit_cstring("\tjmp ");
346 amd64_emit_cfop_target(proj_false);
347 be_emit_finish_line_gas(proj_false);
352 * Emits code for a call.
354 static void emit_be_Call(const ir_node *node)
356 ir_entity *entity = be_Call_get_entity(node);
358 /* %eax/%rax is used in AMD64 to pass the number of vector parameters for
359 * variable argument counts */
360 if (get_method_variadicity (be_Call_get_type((ir_node *) node))) {
361 /* But this still is a hack... */
362 be_emit_cstring("\txor %rax, %rax");
363 be_emit_finish_line_gas(node);
367 be_emit_cstring("\tcall ");
368 be_gas_emit_entity (be_Call_get_entity(node));
369 be_emit_finish_line_gas(node);
371 be_emit_pad_comment();
372 be_emit_cstring("/* FIXME: call NULL entity?! */\n");
379 static void emit_be_Copy(const ir_node *irn)
381 ir_mode *mode = get_irn_mode(irn);
383 if (get_in_reg(irn, 0) == get_out_reg(irn, 0)) {
388 if (mode_is_float(mode)) {
389 panic("emit_be_Copy: move not supported for FP");
390 } else if (mode_is_data(mode)) {
391 be_emit_cstring("\tmov ");
392 amd64_emit_source_register(irn, 0);
393 be_emit_cstring(", ");
394 amd64_emit_dest_register(irn, 0);
395 be_emit_finish_line_gas(irn);
397 panic("emit_be_Copy: move not supported for this mode");
401 static void emit_be_Perm(const ir_node *node)
403 const arch_register_t *in0, *in1;
404 const arch_register_class_t *cls0, *cls1;
406 in0 = arch_get_irn_register(get_irn_n(node, 0));
407 in1 = arch_get_irn_register(get_irn_n(node, 1));
409 cls0 = arch_register_get_class(in0);
410 cls1 = arch_register_get_class(in1);
412 assert(cls0 == cls1 && "Register class mismatch at Perm");
414 be_emit_cstring("\txchg ");
415 amd64_emit_register (in0);
416 be_emit_cstring(", ");
417 amd64_emit_register (in1);
418 be_emit_finish_line_gas(node);
420 if (cls0 != &amd64_reg_classes[CLASS_amd64_gp]) {
421 panic("unexpected register class in be_Perm (%+F)", node);
425 static void emit_amd64_FrameAddr(const ir_node *irn)
427 const amd64_SymConst_attr_t *attr = get_irn_generic_attr_const(irn);
429 be_emit_cstring("\tmov ");
430 amd64_emit_source_register(irn, 0);
431 be_emit_cstring(", ");
432 amd64_emit_dest_register(irn, 0);
433 be_emit_finish_line_gas(irn);
435 be_emit_cstring("\tadd ");
436 be_emit_irprintf("$0x%X", attr->fp_offset);
437 be_emit_cstring(", ");
438 amd64_emit_dest_register(irn, 0);
439 be_emit_finish_line_gas(irn);
443 * Emits code to increase stack pointer.
445 static void emit_be_IncSP(const ir_node *node)
447 int offs = be_get_IncSP_offset(node);
453 be_emit_irprintf("\tsub ");
454 be_emit_irprintf("$%u, ", offs);
455 amd64_emit_dest_register(node, 0);
456 be_emit_finish_line_gas(node);
458 be_emit_irprintf("\tadd ");
459 be_emit_irprintf("$%u, ", -offs);
460 amd64_emit_dest_register(node, 0);
461 be_emit_finish_line_gas(node);
466 * Emits code for a return.
468 static void emit_be_Return(const ir_node *node)
470 be_emit_cstring("\tret");
471 be_emit_finish_line_gas(node);
475 static void emit_amd64_binop_op(const ir_node *irn, int second_op)
477 if (irn->op == op_amd64_Add) {
478 be_emit_cstring("\tadd ");
479 amd64_emit_source_register(irn, second_op);
480 be_emit_cstring(", ");
481 amd64_emit_dest_register(irn, 0);
482 be_emit_finish_line_gas(irn);
483 } else if (irn->op == op_amd64_Sub) {
484 be_emit_cstring("\tneg ");
485 amd64_emit_source_register(irn, second_op);
486 be_emit_finish_line_gas(irn);
487 be_emit_cstring("\tadd ");
488 amd64_emit_source_register(irn, second_op);
489 be_emit_cstring(", ");
490 amd64_emit_dest_register(irn, 0);
491 be_emit_finish_line_gas(irn);
492 be_emit_cstring("\tneg ");
493 amd64_emit_source_register(irn, second_op);
494 be_emit_finish_line_gas(irn);
500 * Emits an arithmetic operation that handles arbitraty input registers.
502 static void emit_amd64_binop(const ir_node *irn)
504 const arch_register_t *reg_s1 = get_in_reg(irn, 0);
505 const arch_register_t *reg_s2 = get_in_reg(irn, 1);
506 const arch_register_t *reg_d1 = get_out_reg(irn, 0);
510 if (reg_d1 != reg_s1 && reg_d1 != reg_s2) {
511 be_emit_cstring("\tmov ");
512 amd64_emit_register(reg_s1);
513 be_emit_cstring(", ");
514 amd64_emit_register(reg_d1);
515 be_emit_finish_line_gas(irn);
518 } else if (reg_d1 == reg_s2 && reg_d1 != reg_s1) {
523 emit_amd64_binop_op(irn, second_op);
527 * The type of a emitter function.
529 typedef void (emit_func)(const ir_node *irn);
532 * Set a node emitter. Make it a bit more type safe.
534 static inline void set_emitter(ir_op *op, emit_func arm_emit_node)
536 op->ops.generic = (op_func)arm_emit_node;
540 * Enters the emitter functions for handled nodes into the generic
541 * pointer of an opcode.
543 static void amd64_register_emitters(void)
545 /* first clear the generic function pointer for all ops */
546 clear_irp_opcodes_generic_func();
548 /* register all emitter functions defined in spec */
549 amd64_register_spec_emitters();
551 set_emitter(op_amd64_SymConst, emit_amd64_SymConst);
552 set_emitter(op_amd64_Jmp, emit_amd64_Jmp);
553 set_emitter(op_amd64_Jcc, emit_amd64_Jcc);
554 set_emitter(op_amd64_Conv, emit_amd64_Conv);
555 set_emitter(op_amd64_FrameAddr, emit_amd64_FrameAddr);
556 set_emitter(op_be_Return, emit_be_Return);
557 set_emitter(op_be_Call, emit_be_Call);
558 set_emitter(op_be_Copy, emit_be_Copy);
559 set_emitter(op_be_IncSP, emit_be_IncSP);
560 set_emitter(op_be_Perm, emit_be_Perm);
562 set_emitter(op_amd64_Add, emit_amd64_binop);
563 set_emitter(op_amd64_Sub, emit_amd64_binop);
565 set_emitter(op_be_Start, emit_nothing);
566 set_emitter(op_be_Keep, emit_nothing);
567 set_emitter(op_be_Barrier, emit_nothing);
568 set_emitter(op_Phi, emit_nothing);
571 typedef void (*emit_func_ptr) (const ir_node *);
574 * Emits code for a node.
576 static void amd64_emit_node(const ir_node *node)
578 ir_op *op = get_irn_op(node);
580 if (op->ops.generic) {
581 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
584 ir_fprintf(stderr, "No emitter for node %+F\n", node);
589 * Walks over the nodes in a block connected by scheduling edges
590 * and emits code for each node.
592 static void amd64_gen_block(ir_node *block, void *data)
597 if (! is_Block(block))
600 be_gas_emit_block_name(block);
603 be_emit_write_line();
605 sched_foreach(block, node) {
606 amd64_emit_node(node);
612 * Sets labels for control flow nodes (jump target)
613 * TODO: Jump optimization
615 static void amd64_gen_labels(ir_node *block, void *env)
618 int n = get_Block_n_cfgpreds(block);
621 for (n--; n >= 0; n--) {
622 pred = get_Block_cfgpred(block, n);
623 set_irn_link(pred, block);
630 void amd64_gen_routine(ir_graph *irg)
632 ir_entity *entity = get_irg_entity(irg);
636 /* register all emitter functions */
637 amd64_register_emitters();
639 blk_sched = be_create_block_schedule(irg);
641 be_dbg_method_begin(entity);
642 be_gas_emit_function_prolog(entity, 4);
644 irg_block_walk_graph(irg, amd64_gen_labels, NULL, NULL);
646 n = ARR_LEN(blk_sched);
647 for (i = 0; i < n; i++) {
648 ir_node *block = blk_sched[i];
649 ir_node *next = (i + 1) < n ? blk_sched[i+1] : NULL;
651 set_irn_link(block, next);
654 for (i = 0; i < n; ++i) {
655 ir_node *block = blk_sched[i];
657 amd64_gen_block(block, 0);
660 be_gas_emit_function_epilog(entity);
663 be_emit_write_line();