1 #if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
3 #define a_barrier a_barrier
4 static inline void a_barrier()
6 __asm__ __volatile__("dmb ish");
10 static inline int a_cas(volatile int *p, int t, int s)
24 : "r"(t), "r"(s), "Q"(*p)
30 static inline int a_swap(volatile int *x, int v)
40 : "=&r"(old), "=&r"(tmp)
46 #define a_fetch_add a_fetch_add
47 static inline int a_fetch_add(volatile int *x, int v)
58 : "=&r"(old), "=&r"(tmp)
65 static inline void a_inc(volatile int *x)
76 : "=&r"(tmp), "=&r"(tmp2)
82 static inline void a_dec(volatile int *x)
93 : "=&r"(tmp), "=&r"(tmp2)
99 static inline void a_and(volatile int *x, int v)
102 __asm__ __volatile__(
110 : "=&r"(tmp), "=&r"(tmp2)
116 static inline void a_or(volatile int *x, int v)
119 __asm__ __volatile__(
127 : "=&r"(tmp), "=&r"(tmp2)
132 #define a_store a_store
133 static inline void a_store(volatile int *p, int x)
135 __asm__ __volatile__(
146 int __a_cas(int, int, volatile int *) __attribute__((__visibility__("hidden")));
147 #define __k_cas __a_cas
149 #define a_barrier a_barrier
150 static inline void a_barrier()
152 __asm__ __volatile__("bl __a_barrier"
153 : : : "memory", "cc", "ip", "lr" );
157 static inline int a_cas(volatile int *p, int t, int s)
161 if (!__k_cas(t, s, p))